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8
H8/3724 Group, H8/3754 Group
Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Series
Rev.3.00 Revision Date: Dec. 1994
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Rev. 3.00, 12/94, page ii of xiv
Preface
The H8/300L Series is a single-chip microcomputer built around the high-speed H8/300L CPU, and equipped with peripheral system functions on chip. The H8/300L CPU has an instruction set compatible with the H8/300 CPU, and is ideal for application to realtime control. The H8/3724 and H8/3754 Series microcomputers are provided with a wide range of peripheral system functions on chip, including a VFD controller/driver five timers, a 14-bit PWM, a twochannel serial communication interface, and an analog-to-digital converter. There are also highvoltage pins for direct VFD driving, making this chip especially suited to use as a microcontroller in an embedded system requiring a VFD display. This manual describes the H8/3724 and H8/3754 Series hardware. Refer to the H8/300L Series Programming Manual for a detailed description of the instruction set.
Rev. 3.00, 12/94, page iii of xiv
Rev. 3.00, 12/94, page iv of xiv
Revised Sections and Contents
Page All All 1 to 4 18 to 20 54 55 91 92 105 112 185 212 218 332 333 Section - - Overview Address Space Notes on Data Access Notes on Bit Manipulation ROM overview Socket Adapter Pin Arrangement and Memory Map RAM overview Notes on Oscillators 14-Bit PWM overview Bit 5 Chip select output select (CS) Application Notes List of Mask Options Rise Time/Fall Time of High-Voltage Pins Revision Contents Description of H8/3753 and H8/3754 added "Pull-down MOS" modified to "pull-down resistor" Description of H8/3753 and H8/3754 added Description of H8/3753 and H8/3754 added Figure modified Description modified Description of H8/3753 and H8/3754 added Description of H8/3753 and H8/3754 added Description of H8/3753 and H8/3754 added Section added Description modified Description modified Description added Description modified including H8/3753 and H8/3754 addition Description modified
Rev. 3.00, 12/94, page v of xiv
Rev. 3.00, 12/94, page vi of xiv
Contents
Section 1
1.1 1.2 1.3
Overview..........................................................................................................
Overview......................................................................................................................... Internal Block Diagram .................................................................................................. Pin Arrangement and Functions ..................................................................................... 1.3.1 Pin Arrangement................................................................................................. 1.3.2 Pin Functions ......................................................................................................
1 1 5 6 6 8
Section 2
2.1
CPU................................................................................................................... 17
17 17 18 21 22 22 22 24 24 25 26 27 27 29 33 35 37 38 38 40 44 46 47 49 49 50 50 50 51 51 52
2.2
2.3
2.4
2.5
2.6
2.7
Overview......................................................................................................................... 2.1.1 Features............................................................................................................... 2.1.2 Address Space..................................................................................................... 2.1.3 Register Configuration........................................................................................ Register Descriptions...................................................................................................... 2.2.1 General Registers................................................................................................ 2.2.2 Control Registers ................................................................................................ 2.2.3 Initial Register Values......................................................................................... Data Formats................................................................................................................... 2.3.1 Data Formats in General Registers ..................................................................... 2.3.2 Memory Data Formats ........................................................................................ Addressing Modes .......................................................................................................... 2.4.1 Addressing Modes .............................................................................................. 2.4.2 Effective Address Calculation ............................................................................ Instruction Set................................................................................................................. 2.5.1 Data Transfer Instructions .................................................................................. 2.5.2 Arithmetic Operations ........................................................................................ 2.5.3 Logic Operations ................................................................................................ 2.5.4 Shift Operations .................................................................................................. 2.5.5 Bit Manipulations ............................................................................................... 2.5.6 Branching Instructions........................................................................................ 2.5.7 System Control Instructions ............................................................................... 2.5.8 Block Data Transfer Instruction ......................................................................... CPU States ...................................................................................................................... 2.6.1 Overview............................................................................................................. 2.6.2 Program Execution State .................................................................................... 2.6.3 Program Halt State.............................................................................................. 2.6.4 Exception-Handling States ................................................................................. Basic Operation Timing.................................................................................................. 2.7.1 Access to On-Chip Memory (RAM, ROM) ....................................................... 2.7.2 Access to On-Chip Peripheral Modules .............................................................
Rev. 3.00, 12/94, page vii of xiv
2.8
Application Notes ........................................................................................................... 53 2.8.1 Notes on Data Access ......................................................................................... 53 2.8.2 Notes on Bit Manipulation.................................................................................. 55
Section 3
3.1 3.2
System Control .............................................................................................. 59
59 59 59 60 62 70 71 71 76 76 77 78 79 80 80 86 87 87 89
3.3
3.4
Overview......................................................................................................................... Exception Handling ........................................................................................................ 3.2.1 Reset ................................................................................................................... 3.2.2 Interrupts............................................................................................................. 3.2.3 Interrupt Control Registers ................................................................................. 3.2.4 External Interrupts .............................................................................................. 3.2.5 Internal Interrupts ............................................................................................... 3.2.6 Operations When an Interrupt is Raised............................................................. 3.2.7 Return from an Interrupt..................................................................................... 3.2.8 Interrupt Response Time..................................................................................... 3.2.9 Valid Interrupts in Each Mode............................................................................ 3.2.10 Notes on Stack Area Use .................................................................................... System Modes................................................................................................................. 3.3.1 Active Mode ....................................................................................................... 3.3.2 Low-Power Operation Mode .............................................................................. 3.3.3 Application Notes ............................................................................................... System Control Registers ............................................................................................... 3.4.1 System Control Register 1 (SYSCR1)................................................................ 3.4.2 System Control Register 2 (SYSCR2)................................................................
Section 4
4.1 4.2
4.3
4.4
4.5
ROM.................................................................................................................. 91 Overview......................................................................................................................... 91 4.1.1 Block Diagram.................................................................................................... 91 PROM Mode................................................................................................................... 92 4.2.1 Setting to PROM Mode ...................................................................................... 92 4.2.2 Socket Adapter Pin Arrangement and Memory Map ......................................... 92 H8/3724ZTAT Programming .......................................................................................... 96 4.3.1 Writing and Verifying ......................................................................................... 96 4.3.2 Precautions When Writing.................................................................................. 99 H8/3726ZTAT Programming .......................................................................................... 100 4.4.1 Writing and Verifying ......................................................................................... 100 4.4.2 Precautions When Writing.................................................................................. 103 Reliability of Written Data ............................................................................................. 104
Rev. 3.00, 12/94, page viii of xiv
Section 5
5.1
RAM ................................................................................................................. 105 Overview......................................................................................................................... 105 5.1.1 Block Diagram.................................................................................................... 105 5.1.2 Display RAM Area ............................................................................................. 106 Clock Pulse Generators ............................................................................... 107 Overview......................................................................................................................... 107 6.1.1 Block Diagram.................................................................................................... 107 System Clock Generator ................................................................................................. 108 Subclock Generator ........................................................................................................ 111 Note on Oscillators ......................................................................................................... 112
Section 6
6.1 6.2 6.3 6.4
Section 7
7.1
7.2
7.3
7.4
7.5
7.6
I/O Ports........................................................................................................... 113 Overview......................................................................................................................... 113 7.1.1 Port Types and Mask Options............................................................................. 115 7.1.2 Pull-Up MOS ...................................................................................................... 116 7.1.3 Pull-Down Resistor............................................................................................. 118 Port 0 ............................................................................................................................ 119 7.2.1 Overview............................................................................................................. 119 7.2.2 Register Configuration and Description ............................................................. 119 7.2.3 Pin Functions ...................................................................................................... 120 7.2.4 Pin States ............................................................................................................ 120 Port 1 ............................................................................................................................ 121 7.3.1 Overview............................................................................................................. 121 7.3.2 Register Configuration and Description ............................................................. 121 7.3.3 Pin Functions ...................................................................................................... 126 7.3.4 Pin States ............................................................................................................ 127 Port 3 ............................................................................................................................ 128 7.4.1 Overview............................................................................................................. 128 7.4.2 Register Configuration and Description ............................................................. 128 7.4.3 Pin Functions ...................................................................................................... 129 7.4.4 Pin States ............................................................................................................ 129 Port 4 ............................................................................................................................ 130 7.5.1 Overview............................................................................................................. 130 7.5.2 Register Configuration and Description ............................................................. 130 7.5.3 Pin Functions ...................................................................................................... 131 7.5.4 Pin States ............................................................................................................ 131 Port 5 ............................................................................................................................ 132 7.6.1 Overview............................................................................................................. 132 7.6.2 Register Configuration and Description ............................................................. 132 7.6.3 Pin Functions ...................................................................................................... 133
Rev. 3.00, 12/94, page ix of xiv
7.7
7.8
7.9
7.10
7.11
7.6.4 Port 6 7.7.1 7.7.2 7.7.3 7.7.4 Port 7 7.8.1 7.8.2 7.8.3 7.8.4 Port 8 7.9.1 7.9.2 7.9.3 7.9.4 Port 9 7.10.1 7.10.2 7.10.3 7.10.4 Port A 7.11.1 7.11.2 7.11.3 7.11.4
Pin States ............................................................................................................ 133 ............................................................................................................................ 134 Overview............................................................................................................. 134 Register Configuration and Description ............................................................. 134 Pin Functions ...................................................................................................... 135 Pin States ............................................................................................................ 135 ............................................................................................................................ 136 Overview............................................................................................................. 136 Register Configuration and Description ............................................................. 136 Pin Functions ...................................................................................................... 137 Pin States ............................................................................................................ 137 ............................................................................................................................ 138 Overview............................................................................................................. 138 Register Configuration and Description ............................................................. 138 Pin Functions ...................................................................................................... 140 Pin States ............................................................................................................ 140 ............................................................................................................................ 141 Overview............................................................................................................. 141 Register Configuration and Description ............................................................. 141 Pin Functions ...................................................................................................... 145 Pin States ............................................................................................................ 147 ............................................................................................................................ 148 Overview............................................................................................................. 148 Register Configuration and Description ............................................................. 148 Pin Functions ...................................................................................................... 149 Pin States ............................................................................................................ 149
Section 8
8.1 8.2
8.3
8.4
Timers............................................................................................................... 151 Overview......................................................................................................................... 151 8.1.1 Prescaler Operation............................................................................................. 152 Timer A........................................................................................................................... 154 8.2.1 Overview............................................................................................................. 154 8.2.2 Register Descriptions.......................................................................................... 155 8.2.3 Timer Operation.................................................................................................. 157 Timer B ........................................................................................................................... 159 8.3.1 Overview............................................................................................................. 159 8.3.2 Register Descriptions.......................................................................................... 160 8.3.3 Timer Operation.................................................................................................. 162 Timer C ........................................................................................................................... 164 8.4.1 Overview............................................................................................................. 164 8.4.2 Register Descriptions.......................................................................................... 165
Rev. 3.00, 12/94, page x of xiv
8.5
8.6
8.7 8.8
8.4.3 Timer Operation.................................................................................................. 168 Timer D........................................................................................................................... 170 8.5.1 Overview............................................................................................................. 170 8.5.2 Register Descriptions.......................................................................................... 171 8.5.3 Timer Operation.................................................................................................. 173 Timer E ........................................................................................................................... 174 8.6.1 Overview............................................................................................................. 174 8.6.2 Register Descriptions.......................................................................................... 176 8.6.3 Timer Operation.................................................................................................. 180 Interrupts......................................................................................................................... 183 Application Notes ........................................................................................................... 183
Section 9
9.1
14-Bit PWM ................................................................................................... 185
9.2
9.3
Overview......................................................................................................................... 185 9.1.1 Features............................................................................................................... 185 9.1.2 Block Diagram.................................................................................................... 185 9.1.3 Pin Configuration................................................................................................ 186 9.1.4 Register Configuration........................................................................................ 186 Register Descriptions...................................................................................................... 187 9.2.1 PWM Control Register (PWCR) ........................................................................ 187 9.2.2 PWM Data Registers U and L (PWDRU, PWDRL) .......................................... 188 Operation ........................................................................................................................ 189
Section 10 SCI1 .................................................................................................................. 191
10.1 Overview......................................................................................................................... 191 10.1.1 Features............................................................................................................... 191 10.1.2 Block Diagram.................................................................................................... 191 10.1.3 Pin Configuration................................................................................................ 192 10.1.4 Register Configuration........................................................................................ 192 Register Descriptions...................................................................................................... 193 10.2.1 Serial Mode Register 1 (SMR1) ......................................................................... 193 10.2.2 Serial Data Register U1 (SDRU1) ...................................................................... 194 10.2.3 Serial Data Register L1 (SDRL1)....................................................................... 195 10.2.4 Serial Port Register 1 (SPR1) ............................................................................. 195 10.2.5 Port Mode Register 2 (PMR2) ............................................................................ 196 10.2.6 Port Mode Register 3 (PMR3) ............................................................................ 197 Operation ........................................................................................................................ 198 10.3.1 Overview............................................................................................................. 198 10.3.2 Data Transfer Format.......................................................................................... 199 10.3.3 Clock................................................................................................................... 199 10.3.4 Data Transmit/Receive........................................................................................ 199
Rev. 3.00, 12/94, page xi of xiv
10.2
10.3
10.3.5 SCI1 State Transitions ........................................................................................ 202 10.3.6 Transfer Clock Error Detection .......................................................................... 203 10.3.7 Interrupts............................................................................................................. 204
Section 11 SCI2 .................................................................................................................. 205
11.1 Overview......................................................................................................................... 205 11.1.1 Features............................................................................................................... 205 11.1.2 Block Diagram.................................................................................................... 205 11.1.3 Pin Configuration................................................................................................ 206 11.1.4 Register Configuration........................................................................................ 206 Register Descriptions...................................................................................................... 207 11.2.1 Start Address Register (STAR)........................................................................... 207 11.2.2 End Address Register (EDAR) ........................................................................... 207 11.2.3 Serial Control Register 2 (SCR2) ....................................................................... 208 11.2.4 Status Register (STSR) ....................................................................................... 209 11.2.5 Port Mode Register 3 (PMR3) ............................................................................ 211 Operation ........................................................................................................................ 213 11.3.1 Overview............................................................................................................. 213 11.3.2 Clock................................................................................................................... 214 11.3.3 Data Transfer Format.......................................................................................... 214 11.3.4 Data Transmit/Receive........................................................................................ 216 Interrupts......................................................................................................................... 218 Application Notes ........................................................................................................... 218
11.2
11.3
11.4 11.5
Section 12 VFD Controller/Driver ................................................................................ 219
12.1 Overview......................................................................................................................... 219 12.1.1 Features............................................................................................................... 219 12.1.2 Block Diagram.................................................................................................... 219 12.1.3 Pin Configuration................................................................................................ 220 12.1.4 Register Configuration........................................................................................ 220 Register Descriptions...................................................................................................... 221 12.2.1 VFD Digital Control Register (VFDR) .............................................................. 221 12.2.2 VFD Segment Control Register (VFSR) ............................................................ 224 12.2.3 Digit Beginning Register (DBR) ........................................................................ 226 Operation ........................................................................................................................ 228 12.3.1 Overview............................................................................................................. 228 12.3.2 Control Part......................................................................................................... 228 12.3.3 RAM Bit Correspondence to Digits/Segments................................................... 228 12.3.4 Procedure for Starting Operation........................................................................ 230 Interrupts......................................................................................................................... 230 Occurrence of Flicker when the VFD Register Is Rewritten.......................................... 230
12.2
12.3
12.4 12.5
Rev. 3.00, 12/94, page xii of xiv
Section 13 A/D Converter................................................................................................ 231
13.1 Overview......................................................................................................................... 231 13.1.1 Features............................................................................................................... 231 13.1.2 Block Diagram.................................................................................................... 232 13.1.3 Pin Configuration................................................................................................ 233 13.1.4 Register Configuration........................................................................................ 233 Register Descriptions...................................................................................................... 234 13.2.1 A/D Result Register (ADRR) ............................................................................. 234 13.2.2 A/D Mode Register (AMR) ................................................................................ 234 13.2.3 A/D Start Register (ADSR) ................................................................................ 237 13.2.4 Port Mode Register 0 (PMR0) ............................................................................ 238 Operation ........................................................................................................................ 238 Interrupts......................................................................................................................... 238 Typical Use ..................................................................................................................... 239 Application Notes ........................................................................................................... 243
13.2
13.3 13.4 13.5 13.6
Section 14 Electrical Specifications.............................................................................. 245
14.1 14.2 Absolute Maximum Ratings ........................................................................................... 245 HD6473724 and HD6473726 Electrical Characteristics................................................ 246 14.2.1 HD6473724 and HD6473726 DC Characteristics.............................................. 246 14.2.2 HD6473724 and HD6473726 AC Characteristics.............................................. 252 14.2.3 HD6473724 and HD6473726 A/D Converter Characteristics............................ 255 HD6433723, HD6433724, HD6433725, HD6433726, HD6433753, and HD6433754 Electrical Characteristics..................................................................... 256 14.3.1 HD6433723, HD6433724, HD6433725, HD6433726, HD6433753, and HD6433754 DC Characteristics .................................................................. 256 14.3.2 HD6433723, HD6433724, HD6433725, HD6433726, HD6433753, and HD6433754 AC Characteristics................................................................... 262 14.3.3 HD6433723, HD6433724, HD6433725, HD6433726, HD6433753, and HD6433754 A/D Converter Characteristics ................................................ 265 Operational Timing......................................................................................................... 266 Differences in Electrical Characteristics between Mask ROM and ZTATTM Versions... 269
14.3
14.4 14.5
Appendix A CPU Instruction Set.................................................................................. 271
A.1 A.2 A.3 Instruction Set List.......................................................................................................... 271 Operation Code Map....................................................................................................... 272 Number of States Required for Execution...................................................................... 274
Appendix B I/O Register Field...................................................................................... 281
B.1 I/O Register Fields (1) .................................................................................................... 281
Rev. 3.00, 12/94, page xiii of xiv
B.2
I/O Register Fields (2) .................................................................................................... 284
Appendix C I/O Port Block Diagrams ......................................................................... 313
C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 Port 0 Block Diagram ..................................................................................................... 313 Port 1 Block Diagram ..................................................................................................... 314 Port 3 Block Diagram ..................................................................................................... 317 Port 4 Block Diagram ..................................................................................................... 318 Port 5 Block Diagram ..................................................................................................... 319 Port 6 Block Diagram ..................................................................................................... 320 Port 7 Block Diagram ..................................................................................................... 321 Port 8 Block Diagram ..................................................................................................... 322 Port 9 Block Diagram ..................................................................................................... 323 Port A Block Diagram .................................................................................................... 329
Appendix D Port States in Each Processing State.................................................... 330 Appendix E List of Mask Options................................................................................. 332 Appendix F Rise Time/Fall Time of High-Voltage Pins......................................... 333 Appendix G External Dimensions................................................................................. 334
Rev. 3.00, 12/94, page xiv of xiv
Section 1 Overview
1.1 Overview
The H8/300L Series is a single-chip microcomputer (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on chip. The H8/3724 and H8/3754 Series are single-chip microcomputers in the H8/300L Series equipped with high-voltage pins. Their on-chip peripheral functions include a vacuum fluorescent display (VFD) controller/driver, timers, a 14-bit PWM (pulse width modulator), two serial communication interface channels, and an analog-to-digital converter. Together these functions make this chip ideally suited to use as a microcontroller in embedded systems requiring a VFD display. The H8/3724 and H8/3754 Series come in the following memory configurations for various system scale needs. H8/3723: H8/3724: H8/3725: H8/3726: H8/3753: H8/3754: 24-kbyte ROM, 384-byte RAM 32-kbyte ROM, 512-byte RAM 40-kbyte ROM, 640-byte RAM 48-kbyte ROM, 1,024-byte RAM 24-kbyte ROM, 1,024-byte RAM 32-kbyte ROM, 1,024-byte RAM
In addition to masked ROM versions available for the H8/3724 Series, H8/3724 and H8/3726 are also available in ZTATTM versions which allow the user to freely program the on-chip PROM. Table 1-1 summarizes the main features of the H8/3724 and H8/3754 Series. Note: * ZTAT (zero turn around time) is a trademark of Hitachi, Ltd.
Rev. 3.00, 12/94, page 1 of 334
Table 1-1 Features
Item CPU Specification Configured of general registers * General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) Operating speed * Max. operating speed: 4.19 MHz * Add/subtract: 0.5 s (operating at = 4 MHz) * Multiply/divide: 3.5 s (operating at = 4 MHz) * Can run on 32 kHz subclock Instruction set compatible with H8/300 CPU * Instruction length of 2 bytes or 4 bytes * Basic arithmetic operations between registers * MOV instruction for data transfer between memory and registers Typical instructions * Multiply (8 bits x 8 bits) * Divide (16 bits / 8 bits) * Bit accumulator * Register-indirect designation of bit position Memory H8/3723: 24-kbyte ROM, 384-byte RAM H8/3724: 32-kbyte ROM, 512-byte RAM H8/3724ZTAT: 32-kbyte EPROM, 512-byte RAM H8/3725: 40-kbyte ROM, 640-byte RAM H8/3726: 48-kbyte ROM, 1,024-byte RAM H8/3726ZTAT: 48-kbyte EPROM, 1,024-byte RAM H8/3753: 24-kbyte ROM, 1,024-byte RAM H8/3754: 32-kbyte ROM, 1,024-byte RAM Timers * Timer A: 8-bit interval timer Timer A can be used as a count-up timer based on any of eight internal clock signals divided from the system clock ()* or four clock signals divided from the subclock (SUB) * Timer B: 8-bit reload timer Timer B can be used as a count-up timer based on any of seven internal clock signals or event input from pin P10/IRQ0
Rev. 3.00, 12/94, page 2 of 334
Table 1-1 Features (cont)
Item Timers Specification * Timer C: 8-bit reload timer Timer C can be used as a count-up/count-down timer based on any of seven internal clock signals or event input from pin P11/IRQ1 * Timer D: 8-bit event counter Timer D is for counting up input from pin P16/EVENT * Timer E: 8-bit reload timer Timer E can be used as a count-up timer based on any of eight internal clock signals. Depending on the setting of pin P15/IRQ5/TMOE, either a fixed frequency output or a duty 50% waveform output indicating timer E overflow is possible Note: * indicates a clock frequency that is divided in half from the original oscillator frequency 14-bit PWM * Pulse-division PWM designed for less ripple * Can be used as a 14-bit D/A converter by connecting to an external lowpass filter VFD controller/driver * Up to 28 segment pins and up to 16 digit pins (of which 8 are for both uses) * Brightness adjustable in 8 steps (dimmer function) * Digit and segment pins can be switched to use as high-voltage I/O pins * Key scan interval can be enabled or disabled * Interrupt can be raised when key scan interval starts Serial communication interface * 2-channel clock-synchronous SCI1 and SCI2 * Choice of 8-bit or 16-bit transfer data (SCI1) * Automatic transfer of 32-byte data (SCI2) * Overrun error detection possible * Interrupt can be raised when transfer is complete A/D converter * Successive approximation using a resistance ladder * Resolution: 8 bits * 8-channel analog input port * Conversion time: 31/ per channel or 62/ * Interrupt can be raised upon completion of A/D conversion
Rev. 3.00, 12/94, page 3 of 334
Table 1-1 Features (cont)
Item I/O ports Specification * High-voltage I/O pins: 36 * High-voltage input pin: 1 * Standard-voltage I/O pins: 24 * Standard-voltage input pins: 9 Interrupts * Six external interrupt pins: IRQ5 to IRQ0 * Ten internal interrupt sources Low-power operation modes * Sleep mode * Standby mode * Watch mode * Subactive mode Product lineup Product Code Mask ROM Version HD6433723H HD6433723F HD6433724H HD6433724F HD6433725H HD6433725F HD6433726H HD6433726F HD6433753H HD6433753F HD6433754H HD6433754F Other ZTAT Version -- -- HD6473724H HD6473724F -- -- HD6473726H HD6473726F -- -- -- -- Package 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) ROM: 32 kbytes RAM: 1,024 bytes ROM: 24 kbytes RAM: 1,024 bytes ROM: 48 kbytes RAM: 1,024 bytes ROM: 40 kbytes RAM: 640 bytes ROM: 32 kbytes RAM: 512 bytes ROM/RAM Size ROM: 24 kbytes RAM: 384 bytes
* Built-in pulse generators for system clock and subclock * Timer A can run on the subclock for use as a time base
Rev. 3.00, 12/94, page 4 of 334
1.2 Internal Block Diagram
Figure 1-1 is an internal block diagram of the H8/3724 and H8/3754 Series.
OSC1 OSC2
TEST RES
VCC
Subclock pulse generator P90 /PWM P91 /SCK1 P9 2 /SI1 P9 3 /SO1 P94 /SCK2 P9 5 /SI 2 /CS P9 6 /SO2 P97 /UD P5 0 /FS15 P5 1 /FS14 P5 2 /FS13 P5 3 /FS12 P5 4 /FS11 P5 5 /FS10 P56 /FS 9 P57 /FS 8 P4 0 /FS16 P4 1 /FS17 P4 2 /FS18 P4 3 /FS19 P4 4 /FS20 P4 5 /FS21 P4 6 /FS22 P4 7 /FS23 P3 0 /FS24 P3 1 /FS25 P3 2 /FS26 P3 3 /FS27
System clock pulse generator
CPU H8/300L P10 /IRQ 0 P11 /IRQ 1 P12 /IRQ 2 P13 /IRQ 3 P14 /IRQ 4 P15 /IRQ 5 /TMOE P16 /EVENT P17 /Vdisp P60 /FD 0 /FS 7 P61 /FD 1 /FS 6 P62 /FD 2 /FS 5 P63 /FD 3 /FS 4 P64 /FD 4 /FS 3 P65 /FD 5 /FS 2 P66 /FD 6 /FS 1 P67 /FD 7 /FS 0 P70 /FD 8 P71 /FD 9 P72 /FD 10 P73 /FD 11 P74 /FD 12 P75 /FD 13 P76 /FD 14 P77 /FD 15 P80 P81 P82 P83 P84 P85 P86 P87
VSS
X1 X2
Data bus (lower) Port 9
RAM
Mask ROM (PROM) Port 5
Timer A Port 6 Port 8 Port 0 AV CC AV SS Port 7
Timer C SCI1 Timer D Port 4 SCI2 Timer E
VFD controller/driver Port 3
14-bit PWM
A/D converter
Port A
PA 0 PA 1
Figure 1-1 Internal Block Diagram
Rev. 3.00, 12/94, page 5 of 334
P00 /AN 0 P01 /AN 1 P02 /AN 2 P03 /AN 3 P04 /AN 4 P05 /AN 5 P06 /AN 6 P07 /AN 7
Address bus
Timer B
Data bus (upper)
Port 1
1.3 Pin Arrangement and Functions
1.3.1 Pin Arrangement The pin arrangements for the H8/3724 and H8/3754 Series are shown in figure 1-2 (FP-80A) and figure 1-3 (FP-80B).
P0 5 /AN 5 P0 4 /AN 4 P0 3 /AN 3 P0 2 /AN 2 P0 1 /AN 1 P0 0 /AN 0 AVCC PA 1 PA 0 P9 7 /UD P9 6 /SO 2 P9 5 /SI2 /CS P9 4 /SCK 2 P9 3 /SO 1 P9 2 /SI1 P9 1 /SCK 1 P9 0 /PWM P8 7 P8 6 P8 5 P0 6 /AN 6 P0 7 /AN 7 AVSS TEST X2 X1 VSS OSC 1 OSC 2 RES P10 /IRQ 0 P11 /IRQ 1 P12 /IRQ 2 P13 /IRQ 3 P14 /IRQ 4 P15 /IRQ 5 /TMOE P16 /EVENT P3 3 /FS 27 P3 2 /FS 26 P3 1 /FS 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P8 4 P8 3 P8 2 P8 1 P8 0 VCC P77 /FD15 P76 /FD14 P75 /FD13 P74 /FD12 P73 /FD11 P72 /FD10 P71 /FD9 P70 /FD8 P6 7 /FD7 /FS 0 P6 6 /FD6 /FS 1 P6 5 /FD5 /FS 2 P6 4 /FD4 /FS 3 P6 3 /FD3 /FS 4 P6 2 /FD2 /FS 5
Figure 1-2 Pin Arrangement (FP-80A: Top view)
Rev. 3.00, 12/94, page 6 of 334
P3 0 /FS 24 P4 7 /FS 23 P4 6 /FS 22 P4 5 /FS 21 P4 4 /FS 20 P4 3 /FS 19 P4 2 /FS 18 P4 1 /FS 17 P4 0 /FS 16 P5 0 /FS 15 P5 1 /FS 14 P5 2 /FS 13 P5 3 /FS 12 P5 4 /FS 11 P5 5 /FS 10 P56 /FS9 P57 /FS8 P17 /Vdisp P6 0 /FD0 /FS7 P6 1 /FD1 /FS6
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P04 /AN 4 P05 /AN 5 P06 /AN 6 P07 /AN 7 AV SS TEST X2 X1 V SS OSC 1 OSC 2 RES P10 /IRQ 0 P11 /IRQ 1 P12 /IRQ 2 P13 /IRQ 3 P14 /IRQ 4 P15 /IRQ 5 /TMOE P16 /EVENT P3 3 /FS 27 P3 2 /FS 26 P3 1 /FS 25 P3 0 /FS 24 P4 7 /FS 23
P0 3 /AN 3 P0 2 /AN 2 P0 1 /AN 1 P0 0 /AN 0 AVCC PA 1 PA 0 P9 7 /UD P9 6 /SO 2 P9 5 /SI2 /CS P9 4 /SCK 2 P9 3 /SO 1 P9 2 /SI1 P9 1 /SCK 1 P9 0 /PWM P8 7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P8 6 P8 5 P8 4 P8 3 P8 2 P8 1 P8 0 VCC P77 /FD15 P76 /FD14 P75 /FD13 P74 /FD12 P73 /FD11 P72 /FD10 P71 /FD9 P70 /FD8 P67 /FD7 /FS 0 P66 /FD6 /FS 1 P65 /FD5 /FS 2 P64 /FD4 /FS 3 P63 /FD3 /FS 4 P62 /FD2 /FS 5 P61 /FD1 /FS 6 P60 /FD0 /FS 7
Figure 1-3 Pin Arrangement (FP-80B: Top view)
P4 6 /FS 22 P4 5 /FS 21 P4 4 /FS 20 P4 3 /FS 19 P4 2 /FS 18 P4 1 /FS 17 P4 0 /FS 16 P5 0 /FS 15 P5 1 /FS 14 P5 2 /FS 13 P5 3 /FS 12 P5 4 /FS 11 P5 5 /FS 10 P5 6 /FS9 P5 7 /FS8 P17 /Vdisp Rev. 3.00, 12/94, page 7 of 334
1.3.2 Pin Functions 1. List of pin functions
Table 1-2 lists the pin functions of the LSI. Table 1-2 List of Pin Functions
Pin No. FP-80A 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 FP-80B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name and Function P04/AN4 (standard input port/analog input channel) P05/AN5 (standard input port/analog input channel) P06/AN6 (standard input port/analog input channel) P07/AN7 (standard input port/analog input channel) AVSS (reference voltage for A/D converter) TEST (test pin) X2 (subclock oscillator connection) X1 (subclock oscillator connection) VSS (ground) OSC1 (system clock oscillator connection) OSC2 (system clock oscillator connection) RES (reset input) P10/IRQ0 (standard I/O port/external interrupt or timer B event input) P11/IRQ1 (standard I/O port/external interrupt or timer C event input) P12/IRQ2 (standard I/O port/external interrupt) P13/IRQ3 (standard I/O port/external interrupt) P14/IRQ4 (standard I/O port/external interrupt) P15/IRQ5/TMOE (standard I/O port/external interrupt/warning tone output) P16/EVENT (standard input port/timer D event input) P33/FS27 (high-voltage I/O port/VFD segment output) P32/FS26 (high-voltage I/O port/VFD segment output) P31/FS25 (high-voltage I/O port/VFD segment output) P30/FS24 (high-voltage I/O port/VFD segment output) P47/FS23 (high-voltage I/O port/VFD segment output) PROM Mode H8/3724 H8/3726 NC NC NC NC VSS VCC NC VCC VSS VCC NC VPP NC NC NC NC NC NC EA9 NC NC NC NC VSS NC NC NC NC VSS VCC NC VCC VSS VCC NC VPP NC NC NC NC NC NC EA9 NC NC NC NC EA16
Rev. 3.00, 12/94, page 8 of 334
Table 1-2 List of Pin Functions (cont)
Pin No. FP-80A 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 FP-80B 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Name and Function P46/FS22 (high-voltage I/O port/VFD segment output) P45/FS21 (high-voltage I/O port/VFD segment output) P44/FS20 (high-voltage I/O port/VFD segment output) P43/FS19 (high-voltage I/O port/VFD segment output) P42/FS18 (high-voltage I/O port/VFD segment output) P41/FS17 (high-voltage I/O port/VFD segment output) P40/FS16 (high-voltage I/O port/VFD segment output) P50/FS15 (high-voltage I/O port/VFD segment output) P51/FS14 (high-voltage I/O port/VFD segment output) P52/FS13 (high-voltage I/O port/VFD segment output) P53/FS12 (high-voltage I/O port/VFD segment output) P54/FS11 (high-voltage I/O port/VFD segment output) P55/FS10 (high-voltage I/O port/VFD segment output) P56/FS9 (high-voltage I/O port/VFD segment output) P57/FS8 (high-voltage I/O port/VFD segment output) P17/Vdisp (high-voltage input port/VFD power source) P60/FD0/FS7 (high-voltage I/O port/VFD digit-segment output) P61/FD1/FS6 (high-voltage I/O port/VFD digit-segment output) P62/FD2/FS5 (high-voltage I/O port/VFD digit-segment output) P63/FD3/FS4 (high-voltage I/O port/VFD digit-segment output) P64/FD4/FS3 (high-voltage I/O port/VFD digit-segment output) P65/FD5/FS2 (high-voltage I/O port/VFD digit-segment output) P66/FD6/FS1 (high-voltage I/O port/VFD digit-segment output) P67/FD7/FS0 (high-voltage I/O port/VFD digit-segment output) P70/FD8 (high-voltage I/O port/VFD digit output) PROM Mode H8/3724 H8/3726 VSS VCC NC VCC VCC VSS VSS EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 VCC NC NC NC NC NC NC NC NC EA8 EA15 PGM NC VCC VCC VSS VSS EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 VCC NC NC NC NC NC NC NC NC EA8
Rev. 3.00, 12/94, page 9 of 334
Table 1-2 List of Pin Functions (cont)
Pin No. FP-80A 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 FP-80B 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Name and Function P71/FD9 (high-voltage I/O port/VFD digit output) P72/FD10 (high-voltage I/O port/VFD digit output) P73/FD11 (high-voltage I/O port/VFD digit output) P74/FD12 (high-voltage I/O port/VFD digit output) P75/FD13 (high-voltage I/O port/VFD digit output) P76/FD14 (high-voltage I/O port/VFD digit output) P77/FD15 (high-voltage I/O port/VFD digit output) VCC (system power source) P80 (standard I/O port) P81 (standard I/O port) P82 (standard I/O port) P83 (standard I/O port) P84 (standard I/O port) P85 (standard I/O port) P86 (standard I/O port) P87 (standard I/O port) P90/PWM (standard I/O port/PWM output) P91/SCK1 (standard I/O port/clock output) P92/SI1 (standard I/O port/data input) P93/SO1 (standard I/O port/data output) P94/SCK2 (standard I/O port/clock I/O) P95/SI2/CS (standard I/O port/data input/chip select output) P96/SO2 (standard I/O port/data output) P97/UD (standard I/O port/Timer C up-down control) PA0 (standard I/O port) PA1 (standard I/O port) AVCC (reference power source for A/D converter) PO0/AN0 (standard input port/analog input channel) PO1/AN1 (standard input port/analog input channel) PROM Mode H8/3724 OE EA10 EA11 EA12 EA13 EA14 CE VCC NC NC NC NC NC NC NC NC EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 NC NC NC NC NC H8/3726 OE EA10 EA11 EA12 EA13 EA14 CE VCC NC NC NC NC NC NC NC NC EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 NC NC NC NC NC
Rev. 3.00, 12/94, page 10 of 334
Table 1-2 List of Pin Functions (cont)
Pin No. FP-80A 77 78 FP-80B 79 80 Name and Function PO2/AN2 (standard input port/analog input channel) PO3/AN3 (standard input port/analog input channel) PROM Mode H8/3724 NC NC H8/3726 NC NC
Notes: 1. NC pins should be left unconnected. 2. Details on PROM mode are given in 4.2, PROM Mode.
2.
Pin functions
Table 1-3 explains the functions of each pin in more detail. Table 1-3 Pin Functions
Pin No. Type Power source pins Symbol FP-80A FP-80B VCC 55 57 I/O Input Name and Functions Power source: Connects to a power source (+5 V) All VCC pins should be connected to the system power source (+5 V). VSS 7 9 Input Ground: Connects to a power source (0 V). All VSS pins should be connected to the system power source (0 V). AVCC 74 76 Input Analog power source: This is the reference power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power source (+5 V). Analog ground: This is the A/D converter ground pin. It should be connected to the system power source (0 V). VFD power source: This pin should be connected to a VFD driver power source. This pin connects to a crystal or ceramic oscillator, or can be used to input an external clock. See section 6, Clock Pulse Generators, for details on connection to a crystal or ceramic oscillator and on external clock input. Rev. 3.00, 12/94, page 11 of 334
AVSS
3
5
Input
Vdisp Clock pins OSC1
38 8
40 10
Input Input
Table 1-3 Pin Functions (cont)
Pin No. Type Clock pins Symbol FP-80A FP-80B OSC2 X1 9 6 11 8 I/O Name and Functions
Output This pin connects to a crystal or ceramic oscillator. Input This pin connects to a 32.768 kHz crystal oscillator. For a typical connection diagram, see section 6, Clock Pulse Generators.
X2 System control RES TEST
5 10 4
7 12 6
Output This pin connects to a 32.768 kHz crystal oscillator. Input Input Reset: When this pin goes to low level, the CPU changes to reset state. Test: This pin is not for use in application systems. It should be connected to a VSS potential. External interrupt request 0: This is an input pin for external interrupts for which there is a choice between rising and falling edge sensing. It can be used to cancel low-power mode. This pin can be used as the event input pin for Timer B. A noise cancel function is also provided.
Interrupt pins
IRQ0
11
13
Input
IRQ1
12
14
Input
External interrupt request 1: This is an input pin for external interrupts for which there is a choice between rising and falling edge sensing. It can be used to cancel low-power mode. This pin can be used as the event input pin for Timer C.
IRQ2
13
15
Input
External interrupt request 2: This is an input pin for external interrupts that are detected at the falling edge. External interrupt request 3: This is an input pin for external interrupts that are detected at the falling edge.
IRQ3
14
16
Input
Rev. 3.00, 12/94, page 12 of 334
Table 1-3 Pin Functions (cont)
Pin No. Type Interrupt pins Symbol FP-80A FP-80B IRQ4 15 17 I/O Input Name and Functions External interrupt request 4: This is an input pin for external interrupts for which there is a choice between rising and falling edge sensing. External interrupt request 5: This is an input pin for external interrupts that are detected at the falling edge. Timer B event counter input: This is an event input pin for input to the Timer B counter. Timer C event counter input: This is an event input pin for input to the Timer C counter. Timer C up/down select: This pin selects whether the Timer C counter is used for count-up or count-down. At high level it selects an up-counter, and at low level a down-counter. Input to this pin is valid only when bit TMC6 in timer mode register C (TMC) is set to 1. EVENT 17 19 Input Timer D event counter input: This is an event input pin for input to the Timer D counter.
IRQ5
16
18
Input
Timer pins
IRQ0
11
13
Input
IRQ1
12
14
Input
UD
71
73
Input
TMOE
16
18
Output Timer E output: This is an output pin for waveforms generated by the Timer E output circuit. Output 14-bit PWM output: This is an output pin for waveforms generated by the 14-bit PWM.
14-bit PWM pin
PWM
64
66
Rev. 3.00, 12/94, page 13 of 334
Table 1-3 Pin Functions (cont)
Pin No. Type Serial communication interface (SCI) pins Symbol FP-80A FP-80B I/O SO1 SO2 SI1 SI2 SCK1 SCK2 CS 67 70 66 69 65 68 69 69 72 68 71 67 70 71 Name and Functions
Output Serial send data output (channels 1 and 2): These are SCI data output pins. Input I/O Serial receive data input (channels 1 and 2): These are SCI data input pins. Serial clock I/O (channels 1 and 2): These are SCI clock I/O pins.
Output Chip select output: When SCI2 is in send mode and the transfer clock is an internal clock, this pin goes to low level. This function is valid when bit SI2 in port mode register 2 (PMR2) is 1 and the CS bit in PMR3 is 1.
I/O ports
P07 to P00 P17 P16 P15 to P10 P33 to P30 P47 to P40 P57 to P50 P67 to P60 P77 to P70 P87 to P80
2, 1, 4 to 1, Input 80 to 75 80 to 77 38 17 40 19 Input Input
Port 0: This is an 8-bit input port. Port 1 (bit 7): This is a 1-bit highvoltage input pin. Port 1 (bit 6): This is a 1-bit input pin. Port 1: This is a 6-bit I/O pin. Input or output can be designated for each bit by means of port control register 1 (PCR1). Port 3: This is a 4-bit high-voltage I/O port. Port 4: This is an 8-bit high-voltage I/O port. Port 5: This is an 8-bit high-voltage I/O port. Port 6: This is an 8-bit high-voltage I/O port. Port 7: This is an 8-bit high-voltage I/O port. Port 8: This is an 8-bit I/O port. Input or output can be designated for each bit by means of PCR8.
16 to 11 18 to 13 I/O
18 to 21 20 to 23 I/O 22 to 29 24 to 31 I/O 37 to 30 39 to 32 I/O 46 to 39 48 to 41 I/O 54 to 47 56 to 49 I/O 63 to 56 65 to 58 I/O
Rev. 3.00, 12/94, page 14 of 334
Table 1-3 Pin Functions (cont)
Pin No. Type I/O ports Symbol FP-80A FP-80B P97 to P90 I/O Name and Functions Port 9: This is an 8-bit I/O port. Input or output can be designated for each bit by means of PCR9. Port A: This is a 2-bit I/O port. Input or output can be designated for each bit by means of PCRA. Analog input channels 7 to 0: These are analog data input channels to the A/D converter.
71 to 64 73 to 66 I/O
PA1, PA0 73, 72
75, 74
I/O
A/D converter
AN7 to AN0 FD15 to FD0 FS27 to FS8 FS7 to FS0
2, 1, 4 to 1, Input 80 to 75 80 to 77
VFD controller
54 to 39 56 to 41 Output VFD digit output: These are digit output pins from the VFD driver/controller. 18 to 37 20 to 39 I/O 39 to 46 41 to 48 VFD segment output: These are segment output pins from the VFD driver/controller. When a key scan interval is set during display operations, these pins can be manipulated by the CPU during this interval as a general I/O port.
Rev. 3.00, 12/94, page 15 of 334
Rev. 3.00, 12/94, page 16 of 334
Section 2 CPU
2.1 Overview
The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise, optimized instruction set is designed for high-speed operation. 2.1.1 Features The main features of the H8/300L CPU are listed below. * Two-way register configuration -- Sixteen 8-bit general registers, or -- Eight 16-bit general registers Instruction set with 55 basic instructions, including: -- Multiply and divide instructions -- Powerful bit-manipulation instructions Eight addressing modes -- Register direct -- Register indirect -- Register indirect with displacement -- Register indirect with post-increment or pre-decrement -- Absolute address -- Immediate -- Program-counter relative -- Memory indirect Rn @Rn @(d:16, Rn) @Rn+ or @-Rn @aa:8 or @aa:16 #xx:8 or #xx:16 @(d:8, PC) @@aa:8
*
*
* *
64-kbyte address space High-speed operation -- All frequently used instructions are executed in two to four states -- High-speed arithmetic and logic operations -- 8- or 16-bit register-register add or subtract: 0.5 s* -- 8 x 8-bit multiply: 3.5 s* -- 16 / 8-bit divide: 3.5 s* Low-power operation modes -- SLEEP instruction for transfer to low-power operation Note: * These values are at = 4 MHz.
*
Rev. 3.00, 12/94, page 17 of 334
2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. The memory map of each H8/3724 and H8/3754 version varies with the ROM size. Figure 2-1 gives the memory maps for the H8/3724 and H8/3754 Series.
H'0000 H'002B
Interrupt vector (44 bytes)
H'0000 H'002B 24,576 bytes
Interrupt vector (44 bytes)
On-chip ROM (24,532 bytes)
On-chip ROM (32,212 bytes)
32,256 bytes
H'5FFF H'7DFF
H'FE00 H'FEC0 H'FF00 H'FF7F H'FF80 H'FF9F H'FFA0 H'FFA3 H'FFA4 H'FFAF H'FFB0
H'FD80 On-chip RAM (192 bytes) Used also for VFD display RAM (64 bytes) On-chip RAM (128 bytes) 32-byte data buffer Internal I/O register (4 bytes) Reserved Internal I/O register (80 bytes) 384 bytes H'FEC0 H'FF00 H'FF7F H'FF80 H'FF9F H'FFA0 H'FFA3 H'FFA4 H'FFAF H'FFB0
On-chip RAM (320 bytes) Used also for VFD display RAM (64 bytes) On-chip RAM (128 bytes) 32-byte data buffer Internal I/O register (4 bytes) Reserved Internal I/O register (80 bytes) 512 bytes
H'FFFF H8/3723
H'FFFF H8/3724
Figure 2-1 Memory Map (1)
Rev. 3.00, 12/94, page 18 of 334
H'0000
Interrupt vector (44 bytes)
H'0000
Interrupt vector (44 bytes)
On-chip ROM (40,916 bytes)
40,960 bytes On-chip ROM (49,108 bytes)
49,152 bytes
H'9FFF H'BFFF
H'FB80 H'FD00 On-chip RAM (448 bytes) H'FEC0 H'FF00 H'FF7F H'FF80 H'FF9F H'FFA0 H'FFA3 H'FFA4 H'FFAF H'FFB0 Used also for VFD display RAM (64 bytes) On-chip RAM (128 bytes) 32-byte data buffer Internal I/O register (4 bytes) Reserved Internal I/O register (80 bytes) H'FFFF H8/3725 H'FFFF H8/3726 640 bytes H'FEC0 H'FF00 H'FF7F H'FF80 H'FF9F H'FFA0 H'FFA3 H'FFA4 H'FFAF H'FFB0 On-chip RAM (832 bytes) 1,024 bytes
Used also for VFD display RAM (64 bytes) On-chip RAM (128 bytes) 32-byte data buffer Internal I/O register (4 bytes) Reserved Internal I/O register (80 bytes)
Figure 2-1 Memory Map (2)
Rev. 3.00, 12/94, page 19 of 334
H'0000
Interrupt vector (44 bytes)
H'0000
Interrupt vector (44 bytes)
On-chip ROM (24,532 bytes)
24,576 bytes On-chip ROM (32,724 bytes)
32,768 bytes
H'5FFF H'7FFF
H'FB80 On-chip RAM (832 bytes) H'FEC0 H'FF00 H'FF7F H'FF80 H'FF9F H'FFA0 H'FFA3 H'FFA4 H'FFAF H'FFB0 1,024 bytes
H'FB80 On-chip RAM (832 bytes) H'FEC0 H'FF00 H'FF7F H'FF80 H'FF9F H'FFA0 H'FFA3 H'FFA4 H'FFAF H'FFB0 1,024 bytes
Used also for VFD display RAM (64 bytes) On-chip RAM (128 bytes) 32-byte data buffer Internal I/O register (4 bytes) Reserved Internal I/O register (80 bytes)
Used also for VFD display RAM (64 bytes) On-chip RAM (128 bytes) 32-byte data buffer Internal I/O register (4 bytes) Reserved Internal I/O register (80 bytes)
H'FFFF H8/3753
H'FFFF H8/3754
Figure 2-1 Memory Map (3)
Rev. 3.00, 12/94, page 20 of 334
2.1.3 Register Configuration Figure 2-2 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers.
General registers (Rn) 7 R0H R1H R2H R3H R4H R5H R6H R7H (SP) 07 R0L R1L R2L R3L R4L R5L R6L R7L SP: Stack pointer 0
Control registers 15 PC 76543210 I UHUNZVC 0 PC: Program counter CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit
CCR
Figure 2-2 CPU Registers
Rev. 3.00, 12/94, page 21 of 334
2.2 Register Descriptions
2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). R7 also functions as the stack pointer, used implicitly by hardware in exception processing and subroutine calls. In assembly-language coding, R7 can also be denoted by the symbol SP. As indicated in figure 2-3, SP (R7) points to the top of the stack.
Lower address side [H'0000]
Unused area SP (R7) Stack area
Upper address side [H'FFFF]
Figure 2-3 Stack Pointer 2.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). 1. Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored (always regarded as 0). Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
2.
Rev. 3.00, 12/94, page 22 of 334
Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For further details, see 3.2.2, Interrupts. Bit 6--User Bit (U): Can be written and read by software for its own purposes (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. The H flag is used implicitly by the DAA and DAS instructions. When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. Bit 4--User Bit (U): Can be written and read by software for its own purposes (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 3--Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. The LDC, STC, ANDC, ORC, and XORC instructions enable the CPU to load and store the CCR, and to set or clear selected bits by logic operations. The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions. Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag bits.
Rev. 3.00, 12/94, page 23 of 334
2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is loaded from the vector table and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. To prevent program crashes the stack pointer should be initialized by software, by the first instruction executed after a reset.
2.3 Data Formats
The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. * Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). All arithmetic instructions except ADDS and SUBS can operate on byte data. The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions operate on word data. The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in packed BCD form. Each nibble of the byte is treated as a decimal digit.
* *
*
Rev. 3.00, 12/94, page 24 of 334
2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-4.
Data Type
Register No.
7
Data Format
0
1-bit data
RnH
7
6
5
4
3
2
1
0
Don't care
7
0
1-bit data
RnL
Don't care
7
6
5
4
3
2
1
0
7
0 LSB
Byte data
RnH
MSB
Don't care
7
0 LSB
Byte data
RnL
Don't care
MSB
15
0 LSB
Word data
Rn
MSB
7
4 Upper digit
3 Lower digit
0
4-bit BCD data
RnH
Don't care
7
4 Upper digit
3 Lower digit
0
4-bit BCD data
RnL
Don't care
Notation: RnH: Upper digit of general register RnL: Lower digit of general register MSB: Most significant bit LSB: Least significant bit
Figure 2-4 Register Data Formats
Rev. 3.00, 12/94, page 25 of 334
2.3.2 Memory Data Formats Figure 2-5 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, the access is performed at the preceding even address. This rule affects the MOV.W instruction, and also applies to instruction fetching. Word access is possible only for the on-chip ROM and RAM areas. For further details, see 2.8.1, Notes on Data Access.
Data Type Address Data Format
7
0
1-bit data Byte data
Address n Address n Even address Odd address Even address Odd address Even address Odd address
7
MSB
6
5
4
3
2
1
0
LSB
Word data
MSB
Upper 8 bits Lower 8 bits LSB
Byte data (CCR) on stack
MSB MSB
CCR CCR*
LSB LSB
Word data on stack
MSB LSB
Note: * Ignored on return Notation: CCR: Condition code register
Figure 2-5 Memory Data Formats When the stack is accessed using R7 as an address register, word access should always be performed. For further details, see 3.2.10, Notes on Stack Area Use. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are restored, the lower byte is ignored.
Rev. 3.00, 12/94, page 26 of 334
2.4 Addressing Modes
2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a subset of these addressing modes. Table 2-1 Addressing Modes
No. 1 2 3 4 5 6 7 8 Address Modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @Rn @(d:16, Rn) @Rn+ @-Rn @aa:8 or @aa:16 #xx:8 or #xx:16 @(d:8, PC) @@aa:8
1.
Register Direct--Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions have 16-bit operands.
2.
Register Indirect--@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand. Register Indirect with Displacement--@(d:16, Rn): The instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address. This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address must be even.
3.
Rev. 3.00, 12/94, page 27 of 334
4.
Register Indirect with Post-Increment or Pre-Decrement--@Rn+ or @-Rn: * Register indirect with post-increment--@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. * Register indirect with pre-decrement--@-Rn The @-Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. The register retains the decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the register must be even.
5.
Absolute Address--@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is H'FF00 to H'FFFF (65280 to 65535).
6.
Immediate--#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number.
7.
Program-Counter Relative--@(d:8, PC): This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. The possible branching range is -126 to +128 bytes (-63 to +64 words) from the current address. The displacement should be an even number.
Rev. 3.00, 12/94, page 28 of 334
8.
Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/3724 and H8/3754 Series, addresses H'0000 to H'002B (0 to 43) are located in the vector table. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See 2.3.2, Memory Data Formats, for further information.
2.4.2 Effective Address Calculation Table 2-2 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing 1. The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing 6. Data transfer instructions can use all addressing modes except program-counter relative 7 and memory indirect 8. Bit manipulation instructions use register direct 1, register indirect 2, or absolute 5 addressing to specify a byte operand, and 3-bit immediate addressing 6 to specify a bit position in that byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing 1 to specify the bit position.
Rev. 3.00, 12/94, page 29 of 334
Table 2-2 Effective Address Calculation
Effective Address Calculation Method
3 0 3 0
No. rm
43 0
Addressing Mode and Instruction Format Effective Address (EA) rn
1
Register direct, Rn
15
87
op
15 0
rm
Contents (16 bits) of register indicated by rm
15 43 0
rn
Operand is contents indicated by rm/rn.
0
Rev. 3.00, 12/94, page 30 of 334 rm
15 0
2
Register indirect, @Rn
15
76
op
3
Contents (16 bits) of register indicated by rm
43 0
Register indirect with displacement, @(d:16, Rn) rm disp
15
0
15
76
op
disp
15 0 15 0
4
43 0
Register indirect with post-increment, @Rn+ rm
Contents (16 bits) of register indicated by rm
15
76
op
15
1 or 2
0
Register indirect with pre-decrement, @-Rn
43 0
Contents (16 bits) of register indicated by rm
15
0
15
76
op
rm
Incremented or decremented by 1 if operand is byte size, 1 or 2 and by 2 if word size.
Table 2-2 Effective Address Calculation (cont)
Effective Address Calculation Method
15 87
No. H'FF
0
Addressing Mode and Instruction Format Effective Address (EA)
5
Absolute address @aa:8 abs
15 0
0
15
87
op
@aa:16
0
15
op
abs
6
0
Immediate #xx:8 IMM Operand is 1- or 2-byte immediate data.
0
15
87
op
#xx:16
15
op
IMM
15 0
7
Program-counter relative @(d:8, PC)
PC contents
15
0
15
87
0
Sign extension
disp
Rev. 3.00, 12/94, page 31 of 334 disp
op
Table 2-2 Effective Address Calculation (cont)
Effective Address Calculation Method Effective Address (EA)
No.
Addressing Mode and Instruction Format
8
0
Memory indirect, @@aa:8
15
87
op
15 87 0
abs H'00
15
Rev. 3.00, 12/94, page 32 of 334 abs
0
Memory contents (16 bits)
Notation: rm, rn: Register field Operation field op: disp: Displacement IMM: Immediate data abs: Absolute address
2.5 Instruction Set
The H8/300L CPU can use a total of 55 instructions, which are grouped by function in table 2-3. Table 2-3 Instruction Set
Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data transfer Instructions MOV, PUSH*1, POP*1 Types 1 14 4 8 14 5 8 1 Total: 55 Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @-SP. POP Rn is equivalent to MOV.W @SP+, Rn. 2. Bcc is a conditional branch instruction in which cc represents a condition code.
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*2, JMP, BSR, JSR, RTS RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV
The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next.
Rev. 3.00, 12/94, page 33 of 334
Notation
Rd Rs Rn (EAd) (EAs) CCR N Z V C PC SP #IMM disp + - x / :3 :8 :16 ()< > General register (destination) General register (source) General register Destination operand Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Inverse logic (logical complement) 3-bit length 8-bit length 16-bit length Contents of operand effective address
Rev. 3.00, 12/94, page 34 of 334
2.5.1 Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-6 shows their object code formats. Table 2-4 Data Transfer Instructions
Instruction MOV Size* B/W Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @-Rn, and @Rn+ addressing modes are available for byte or word data. The @aa:8 addressing mode is available for byte data only. The @-R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. PUSH W Rn @-SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @-SP. POP W @SP+ Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn. Notes: * Size: Operand size B: Byte W: Word
Certain precautions are required in data access. See 2.8.1, Notes on Data Access, for details.
Rev. 3.00, 12/94, page 35 of 334
15
8
7
0
MOV RmRn
op
15 8 7
rm
rn
0
op
15 8 7
rm
rn
0
@RmRn
op disp
15 8 7
rm
rn
@(d:16, Rm)Rn
0
op
15 8 7
rm
rn
0
@Rm+Rn, or Rn @-Rm
op
15
rn
8 7
abs
0
@aa:8Rn
op abs
15 8 7
rn
@aa:16Rn
0
op
15
rn
8 7
IMM
0
#xx:8Rn
op IMM
15 8 7
rn
#xx:16Rn
0
op Notation: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data
1
1
1
rn
PUSH, POP @SP+ Rn, or Rn @-SP
Figure 2-6 Data Transfer Instruction Codes
Rev. 3.00, 12/94, page 36 of 334
2.5.2 Arithmetic Operations Table 2-5 describes the arithmetic instructions. Table 2-5 Arithmetic Instructions
Instruction ADD SUB Size* B/W Function Rd Rs Rd, Rd + #IMM Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. Rd 1 Rd Increments or decrements a general register. Rd 1 Rd, Rd 2 Rd Adds or subtracts immediate data to or from data in a general register. The immediate data must be 1 or 2. Rd decimal adjust Rd Decimal-adjusts (adjusts to packed BCD) an addition or subtraction result in a general register by referring to the CCR. B Rd x Rs Rd Performs 8-bit x 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result. Rd / Rs Rd Performs 16-bit / 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR according to the result. Word data can be compared only between two general registers. 0 - Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register.
ADDX SUBX
B
INC DEC ADDS SUBS DAA DAS
B W
B
MULXU
DIVXU
B
CMP
B/W
NEG
B
Notes: * Size: Operand size B: Byte W: Word
Rev. 3.00, 12/94, page 37 of 334
2.5.3 Logic Operations Table 2-6 describes the four instructions that perform logic operations. Table 2-6 Logic Operation Instructions
Instruction AND Size* B Function Rd Rs Rd, Rd #IMM Rd
Performs a logical AND operation on a general register and another general register or immediate data. OR B Rd Rs Rd, Rd #IMM Rd
Performs a logical OR operation on a general register and another general register or immediate data. XOR B Rd Rs Rd, Rd #IMM Rd
Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B ~ Rd Rd Obtains the one's complement (logical complement) of general register contents. Notes: * Size: Operand size B: Byte
2.5.4 Shift Operations Table 2-7 describes the eight shift instructions. Table 2-7 Shift Instructions
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Size* B Function Rd shift Rd Performs an arithmetic shift operation on general register contents. B Rd shift Rd Performs a logical shift operation on general register contents. B Rd rotate Rd Rotates general register contents. B Rd rotate through carry Rd Rotates general register contents through the C (carry) bit.
Notes: * Size: Operand size B: Byte
Rev. 3.00, 12/94, page 38 of 334
Figure 2-7 shows the instruction code format of arithmetic, logic, and shift instructions.
15 8 7 0
op
15 8 7
rm
rn
0
ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT
0
op
15 8 7
rn
op
15 8 7
rm
rn
0
MULXU, DIVXU
op
15
rn
8 7
IMM
0
ADD, ADDX, SUBX, CMP (#XX:8)
op
15 8 7
rm
rn
0
AND, OR, XOR (Rm)
op
15
rn
8 7
IMM
0
AND, OR, XOR (#xx:8)
op Notation: op: Operation field rm, rn: Register field IMM: Immediate data
rn
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Figure 2-7 Arithmetic, Logic, and Shift Instruction Codes
Rev. 3.00, 12/94, page 39 of 334
2.5.5 Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-8 shows their object code formats. Table 2-8 Bit-Manipulation Instructions
Instruction BSET Size* B Function 1 ( of ) Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 ( of ) Clears a specified bit in a general register or memory to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ~ ( of ) ( of ) Inverts a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ~ ( of ) Z Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C ( of ) C ANDs the C flag with a specified bit in a general register or memory and stores the result in the carry flag. BIAND B C [~ ( of )] C ANDs the C flag with the inverse of a specified bit in a general register or memory and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C ( of ) C ORs the C flag with a specified bit in a general register or memory and stores the result in the carry flag. BIOR B C [~ ( of )] C ORs the C flag with the inverse of a specified bit in a general register or memory and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. Notes: * Size: Operand size B: Byte
Rev. 3.00, 12/94, page 40 of 334
Table 2-8 Bit-Manipulation Instructions (cont)
Instruction BXOR Size* B Function C ( of ) C XORs the C flag with a specified bit in a general register or memory and stores the result in the carry flag. BIXOR B C ~ [( of )] C XORs the C flag with the inverse of a specified bit in a general register or memory and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B ( of ) C Copies a specified bit in a general register or memory to the C flag. BILD B ~ ( of ) C Copies the inverse of a specified bit in a general register or memory to the C flag. The bit number is specified by 3-bit immediate data. BST B C ( of ) Copies the C flag to a specified bit in a general register or memory. BIST B ~ C ( of ) Copies the inverse of the C flag to a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. Notes: * Size: Operand size B: Byte
Certain precautions are required in bit manipulation. See 2.8.2, Notes on Bit Manipulation, for details.
Rev. 3.00, 12/94, page 41 of 334
BSET, BCLR, BNOT, BTST
15 8 7 0
op
15 8 7
IMM
rn
0
Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm)
0
op
15 8 7
rm
rn
op op
15 8 7
rn IMM
0 0
0 0
0 0
0 Operand: register indirect (@Rn) 0 Bit No.:
0
immediate (#xx:3)
op op
15 8 7
rn rm
0 0
0 0
0 0
0 Operand: register indirect (@Rn) 0 Bit No.:
0
register direct (Rm)
op op
15 8 7
abs IMM 0 0 0
Operand: absolute (@aa:8) 0 Bit No.:
0
immediate (#xx:3)
op op rm
abs 0 0 0
Operand: absolute (@aa:8) 0 Bit No.: register direct (Rm)
BAND, BOR, BXOR, BLD, BST
15 8 7 0
op
15 8 7
IMM
rn
0
Operand: register direct (Rn) Bit No.: immediate (#xx:3)
op op
15 8 7
rn IMM
0 0
0 0
0 0
0 Operand: register indirect (@Rn) 0 Bit No.:
0
immediate (#xx:3)
op op IMM
abs 0 0 0
Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3)
Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data
Figure 2-8 Bit Manipulation Instruction Codes
Rev. 3.00, 12/94, page 42 of 334
BIAND, BIOR, BIXOR, BILD, BIST
15 8 7 0
op
15 8 7
IMM
rn
0
Operand: register direct (Rn) Bit No.: immediate (#xx:3)
op op
15 8 7
rn IMM
0 0
0 0
0 0
0 Operand: register indirect (@Rn) 0 Bit No.:
0
immediate (#xx:3)
op op IMM
abs 0 0 0
Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3)
Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data
Figure 2-8 Bit Manipulation Instruction Codes (cont)
Rev. 3.00, 12/94, page 43 of 334
2.5.6 Branching Instructions Table 2-9 describes the branching instructions. Table 2-9 Branching Instructions
Instruction Bcc Size -- Function Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP JSR BSR RTS -- -- -- -- Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1
Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified displacement from the current address. Returns from a subroutine.
Rev. 3.00, 12/94, page 44 of 334
15
8
7
0
op
15
cc
8 7
disp
0
Bcc
op
15 8 7
rm
0
0
0
0
0
JMP (@Rm)
op abs
15 8 7 0
JMP (@aa:16)
op
15 8 7
abs
0
JMP (@@aa:8)
op
15 8 7
disp
0
BSR
op
15 8 7
rm
0
0
0
0
0
JSR (@Rm)
op abs
15 8 7 0
JSR (@aa:16)
op
15 8 7
abs
0
JSR (@@aa:8)
op Notation: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address
RTS
Figure 2-9 Branching Instruction Codes
Rev. 3.00, 12/94, page 45 of 334
2.5.7 System Control Instructions Table 2-10 describes the system control instructions. Figure 2-10 shows their object code formats. Table 2-10 System Control Instructions
Instruction RTE SLEEP Size* -- -- Function Returns from an exception-handling routine. When this instruction is executed in active mode, the CPU goes to low-power operation mode (sleep mode, standby mode, or watch mode). From subactive mode the state goes to watch mode, or goes back to active mode via watch mode. For details, see 3.3, System Modes. Rs CCR, #IMM CCR Moves immediate data or general register contents to the condition code register. STC B CCR Rd Copies the condition code register to a specified general register. ANDC B CCR #IMM CCR Logically ANDs the condition code register with immediate data. ORC B CCR #IMM CCR Logically ORs the condition code register with immediate data. XORC B CCR #IMM CCR Logically exclusive-ORs the condition code register with immediate data. NOP -- PC + 2 PC Only increments the program counter. Notes: * Size: Operand size B: Byte
LDC
B
Rev. 3.00, 12/94, page 46 of 334
15
8
7
0
op
15 8 7 0
RTE, SLEEP, NOP
op
15 8 7
rn
0
LDC, STC (Rn)
op
IMM
ANDC, ORC, XORC, LDC (#xx:8)
Notation: op: Operation field rn: Register field IMM: Immediate data
Figure 2-10 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2-11 describes the block data transfer instruction. Figure 2-11 shows its object code format. Table 2-11 Block Data Transfer Instruction
Instruction EEPMOV Size -- Function If R4L 0 then repeat until else next; Moves a data block according to parameters set in general registers R4L, R5, and R6. R4L: Size of block (bytes) R5: R6: Starting source address Starting destination address @R5+ @R6+ R4L - 1 R4L R4L = 0
Execution of the next instruction starts as soon as the block transfer is completed.
Rev. 3.00, 12/94, page 47 of 334
15
8
7
0
op op Notation: op: Operation field
Figure 2-11 Block Data Transfer Instruction Code Notes on EEPMOV Instruction 1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6.
R5 R6
R5 + R4L
R6 + R4L
2.
When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction.
R5 R6
R5 + R4L
H'FFFF Not allowed
R6 + R4L
Rev. 3.00, 12/94, page 48 of 334
2.6 CPU States
2.6.1 Overview There are three CPU states, namely, program execution state, program halt state, and exceptionhandling state. Program execution state includes active mode and subactive mode. In program halt state there are sleep mode, standby mode, and watch mode. These states are shown in figure 2-12. Figure 2-13 shows the state transitions.
State
Program execution state
Active mode The CPU executes successive program instructions, synchronized by the system clock. Subactive mode The CPU executes successive program instructions in low-speed operations, synchronized by the subclock.
Low power operation modes
Program halt state A state in which some or all of the chip functions are stopped to conserve power.
Sleep mode
Standby mode
Watch mode Exceptionhandling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt.
Figure 2-12 CPU Operation States
Rev. 3.00, 12/94, page 49 of 334
Reset cleared Reset state Reset occurs Exception-handling state
Reset occurs
Reset occurs
Interrupt source
Exception- Exceptionhandling handling request complete
Program halt state SLEEP instruction executed
Program execution state
Note: On the transitions between modes, see 3.3, System Modes.
Figure 2-13 State Transitions 2.6.2 Program Execution State In program execution state the CPU executes program instructions in sequence. There are two modes in this state, active mode and subactive mode. Operation is synchronized with the system clock in active mode, and with a subclock in subactive mode. For details on these modes, see 3.3, System Modes. 2.6.3 Program Halt State In program halt state there are three modes, namely, sleep mode, standby mode, and watch mode. For details on these modes, see 3.3, System Modes. 2.6.4 Exception-Handling States Exception-handling states are transient states occurring when exception handling is raised by a reset or interrupt, and the CPU changes its normal processing flow. In exception handling caused by an interrupt, PC and CCR values are saved with reference to SP (R7). For details on interrupt handling, see 3.2.2, Interrupts.
Rev. 3.00, 12/94, page 50 of 334
2.7 Basic Operation Timing
CPU operation is synchronized by a clock ( or SUB). In active mode it means , and in subactive mode it means SUB. For details, see section 6, Clock Pulse Generators. The period from the rising edge of or SUB to the next rising edge is called one state. A memory cycle or bus cycle consists of two states; access to on-chip memory and to on-chip peripheral modules always takes place in two states. 2.7.1 Access to On-Chip Memory (RAM, ROM) Two-state access is employed so that high-speed access can be made to on-chip memory. The data bus width is 16 bits, allowing access in byte or word size. Figure 2-14 shows the on-chip memory access cycle.
Bus cycle T1 state or SUB T2 state
Internal address bus
Address
Internal read signal Internal data bus (read access)
Read data
Internal write signal Internal data bus (write access)
Write data
Figure 2-14 On-Chip Memory Access Cycle
Rev. 3.00, 12/94, page 51 of 334
2.7.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states. The data bus width is 8 bits, so access is made in byte size only. This means that two instructions must be used for a word size data access. Figure 2-15 shows the on-chip peripheral module access cycle.
Bus cycle T1 state or SUB T2 state
Internal address bus
Address
Internal read signal Internal data bus (read access)
Read data
Internal write signal Internal data bus (write access)
Write data
Figure 2-15 On-Chip Peripheral Module Access Cycle
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2.8 Application Notes
The following points are to be observed in using the H8/300L CPU. 2.8.1 Notes on Data Access 1. The address space of the H8/300L CPU includes some empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur. Transfer from CPU to empty area: The transferred data will be lost. This action may also cause the CPU to misoperate. Transfer from empty area to CPU: The transferred data cannot be guaranteed. 2. Internal data transfer with on-chip modules other than ROM and RAM areas makes use of an 8-bit data width. If word access is attempted to these areas, the following results will occur. Word access from CPU to I/O register area: Upper bytes: will be written to I/O register. Lower bytes: transferred data will be lost. Word access from I/O register to CPU: Upper bytes: Will be written to upper part of CPU internal register. Lower bytes: Data written to lower part of CPU internal register cannot be guaranteed. Byte size instructions should therefore be used when transferring data with I/O registers other than the on-chip ROM and RAM areas. Figure 2-16 shows the data size in which access can be made with on-chip peripheral modules.
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Access Word Byte Interrupt vector (44 bytes)
On-chip ROM
On-chip RAM Used also for VFD display RAM (64 bytes) On-chip RAM 32-byte data buffer Internal I/O register (4 bytes) Reserved Internal I/O register (80 bytes)
x x x x
Figure 2-16 Data Size for Access to and from On-Chip Peripheral Modules
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2.8.2 Notes on Bit Manipulation The H8/300L CPU executes bit manipulation instructions BSET, BCLR, BNOT, BST, and BIST 8 bits at a time, in the order read modify write. When bit manipulation instructions are executed in the cases illustrated below, care must be taken since the operation may affect other bits besides those being manipulated. 1. Bit manipulation in two registers assigned to the same address (when the source and destination are different)
Example 1: Timer load register and timer counter In this example, a bit manipulation instruction is executed in the timer load register and timer counter of a reload timer. Since the timer load register and timer counter share the same address, the operations take place as follows. a. b. Read: Timer counter value at the time is read. Modify: The CPU manipulates (sets or resets) the bit designated with the instruction. (Other bits remain the same.) Write: The modified data is written to the timer load register.
c.
The timer counter continues to count during this time based on system clock , so the value read from it is not necessarily the same as that in the timer load register. As a result, it is possible that a different value will be written to another bit besides that designated with the instruction. Figure 2-17 shows the reload timer configuration.
Internal bus
R Timer counter Reload Timer load register W
R: Read W: Write
Figure 2-17 Reload Timer Configuration Example 2: Port data register (pin input and data register) When a bit manipulation instruction is executed designating a port data register, the possibility exists that, in addition to the bit designated with the instruction there will be changes in other pin I/O states or other data register contents.
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As noted above, the H8/300L CPU executes bit manipulation instructions 8 bits at a time, in the order read modify write. Since the same address is used for the I/O port data register and the read portion of pin input, a bit manipulation instruction designating a port functions as follows.
x High-voltage pin: pin other than the modified bit
* When set as an input pin (data register = 0) First the CPU reads the pin input level (read), then it sets or resets the designated bit (modify; other bits remain the same), and writes that value to the data register (write). If the input level is high (read data = 1), a value of 1 is written to the data register, changing the input pin to an output pin (high-level output). If the input level is low, no change occurs. * When set as an output pin (data register = 1, high-level output) If the output level is higher than the input high level (VIH), there is no change. If the output level is lower than the input low level (VIL), a value of 0 is written to the data register, so that the PMOS buffer is turned off resulting in pull-down (low level) or highimpedance state. If a load is applied so that the output level is pulled down to a medium level, the resulting state is indeterminate.
y Standard-voltage pin: pin other than the modified bit
* When set as an input pin The CPU reads the pin input level and writes that value to the data register, which may or may not result in a change to the data register contents. * When set as an output pin The data register is read, so no change occurs. 2. Bit manipulation in a register containing a write-only bit
Example: PWM data register, etc. (Note that read and write characteristics can differ from bit to bit.) In this case there is no register (on the source side) to be read, so a bit other than the designated bit takes a value of 1.
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Table 2-12 lists the registers that share the same address, while table 2-13 lists the registers that contain write-only bits. Table 2-12 Registers Assigned to the Same Address
Register Name Timer load register B/Timer counter B Timer load register C/Timer counter C Timer load register E/Timer counter E Port data register 1* Port data register 3* Port data register 4* Port data register 5* Port data register 6* Port data register 7* Port data register 8* Port data register 9* Port data register A* Abbreviation TLB/TCE TLC/TCC TLE/TCE PDR1 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA Address H'FFC3 H'FFC5 H'FFC9 H'FFD1 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDA
Note: * These port data registers are used also for pin input.
Table 2-13 Registers with Write-Only Bits
Register Name Serial mode register 1 PWM control register PWM data register U PWN data register L Port control register 1 Port control register 8 Port control register 9 Port control register A Port mode register 0 Timer mode register D*1 System control register 2*2 Abbreviation SMR1 PWCR PWDRU PWDRL PCR1 PCR8 PCR9 PCRA PMR0 TMD SYSCR2 Address H'FFB0 H'FFCC H'FFCD H'FFCE H'FFE1 H'FFE8 H'FFE9 H'FFEA H'FFEF H'FFC6 H'FFF1
Notes: 1. Only bit CRL (bit 7) is write-only. 2. Bit DTON (bit 3) is a write-only bit only in subactive mode. In active mode it cannot be read or written.
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Section 3 System Control
3.1 Overview
This chapter explains reset state, exception handling, and system modes.
3.2 Exception Handling
Exception handling includes processing of reset exceptions and of interrupts. Table 3-1 summarizes the factors causing each kind of exception, and their priorities. Reset exception handling has the highest priority. Table 3-1 Types of Exception Handling and Priorities
Priority High Exception Source Reset Interrupt Low Timing for Start of Exception Handling Reset exception handling starts as soon as RES pin changes from low to high. When interrupt request is made, interrupt exception handling starts after execution of present instruction is completed.
3.2.1 Reset When the RES pin goes to low level, all processing stops and the system goes to reset state. CPU internal states and each of the registers of on-chip peripheral modules are initialized. The I bit of the condition code register (CCR) is set, masking all interrupts. As soon as the RES pin goes from low to high level, reset exception handling starts. In this processing, the contents indicated by the reset exception handling vector address (H'0000 to H'0001) are read and sent to the program counter (PC). Then program execution starts from the address indicated in PC. Figure 3-1 shows the reset sequence. Notes: 1. To make sure a reset is carried out properly, when power is turned on the RES pin should be kept at low level for at least 20 ms after the power supply starts up. 2. When resetting during operation, keep the RES pin at low level for at least 10 system clock cycles. 3. After a reset, if an interrupt request is received before the stack pointer (SP: R7) has been initialized, PC and CCR values will not be saved properly, causing program runaway operation. To prevent this, all interrupts are disabled right after reset exception handling is executed. Application programs should thus include a step clearing all interrupt masks after SP initialization. An even-numbered address must be set in SP. It is recommended that application programs start with an instruction initializing SP (e.g., MOV.W #xx:16, SP).
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Reset state
Reset exception handling and program execution Prefetch of first instruction of program
Vector fetch RES
Internal processing
Internal address bus Internal read signal Internal write signal Internal data bus (16 bits)
(1)
(2)
(2) (1) Reset exception handling vector address (H'0000) (2) Program starting address (3) First instruction of program
(3)
Figure 3-1 Reset Sequence 3.2.2 Interrupts Factors causing interrupt exception handling to start may be either external interrupts (IRQ5 to IRQ0), or internal interrupts when an on-chip peripheral module makes an interrupt request. Table 3-2 shows the interrupt sources and their priorities, along with the vector addresses. When more than one interrupt is raised, that with the highest priority is processed. 1. Both internal and external interrupts (IRQ5 to IRQ0) can be masked by the I bit of CCR. When this bit is set to 1, the interrupt request flag is set but interrupts cannot be accepted. The external interrupt pins IRQ4, IRQ1, and IRQ0 can each be set independently to either rising edge sensing or falling edge sensing. The remaining external interrupt pins, IRQ5, IRQ3, and IRQ2, are fixed at falling edge sensing.
2.
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Table 3-2 Interrupt Sources
Priority High Interrupt Reset (Reserved)*1 Origin of Interrupt External pin -- Vector Starting Address H'0000 H'0002 H'0004 H'0006 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Key scan Timer A overflow Timer B overflow Timer C overflow Timer D overflow Timer E overflow Direct state transition (Reserved)*1 VFD Timer A Timer B Timer C Timer D Timer E Circuit waiting for oscillator stabilization*2 -- External pin H'0008 H'000A H'000C H'000E H'0010 H'0012 H'0014 H'0016 H'0018 H'001A H'001C H'001E H'0020 H'0022 H'0024 SCI1 transfer complete, error SCI2 transfer complete, error Low A/D conversion complete Serial communication interface 1 Serial communication interface 2 A/D converter H'0026 H'0028 H'002A
Notes: 1. Vector addresses indicated as "Reserved" cannot be used. 2. A circuit for which a SLEEP instruction has been issued, and for which an interrupt request is raised after the stipulated time period.
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3.2.3 Interrupt Control Registers Table 3-3 lists the registers that are used to control interrupts. Table 3-3 Interrupt Control Registers
Register Name Port mode register 1 IRQ edge select register Interrupt enable register 1 Interrupt enable register 2 Interrupt enable register 3 Interrupt request register 1 Interrupt request register 2 Interrupt request register 3 Abbreviation PMR1 IEGR IENR1 IENR2 IENR3 IRR1 IRR2 IRR3 R/W R/W R/W R/W R/W R/W R/W* R/W* R/W* Initial Value H'00 H'EC H'C0 H'00 H'3C H'C0 H'00 H'3C Address H'FFEB H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFF8
Note: * Write is enabled only for writing of 0 to clear flag.
1.
Bit
Port mode register 1 (PMR1)
7
NOISE CANCEL
6 EVENT 0 R/W
5 IRQC5 0 R/W
4 IRQC4 0 R/W
3 IRQC3 0 R/W
2 IRQC2 0 R/W
1 IRQC1 0 R/W
0 IRQC0 0 R/W
Initial value Read/Write
0 R/W
PMR1 is an 8-bit read/write register, for selecting whether the port 1 pin is to be used as an I/O port or as an input port for external interrupts. It is also used to turn on or off the noise canceller function of pin IRQ0. Note: Before switching pin functions using bits IRQ5 to IRQ0 in PMR1, first set the interrupt enable flag to disable interrupts. After the pin functions have been switched, issue any instruction to clear the interrupt request flag to 0. Program example:
MOV. B R0L, @IENR1 MOV. B R0L, @PMR1 NOP MOV. B R0L, @IRR1 MOV. B R1L, @IENR1
...................... Mask interrupts ...................... Change pin function ...................... Issue any instruction ...................... Clear interrupt request flag ...................... Enable interrupts
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Bit 7: Noise cancel (NOISE CANCEL) This bit sets the noise canceller function of pin IRQ0 to on or off.
Bit 7 NOISE CANCEL 0 1 Description Sets the noise canceller function of pin IRQ0 to off. (initial value)
Sets the noise canceller function of pin IRQ0 to on. Input is double-sampled at intervals of 256 states. If the input values do not match, noise is assumed.
Bit 6: P16/EVENT pin function switch (EVENT)
Bit 6 EVENT 0 1 Description P16/EVENT pin functions as P16 pin. P16/EVENT pin functions as EVENT pin. (initial value)
Bit 5: P15/IRQ5/TMOE pin function switch (IRQC5)
Bit 5 IRQC5 0 1 Description P15/IRQ5/TMOE pin functions as P15/TMOE pin.* P15/IRQ5/TMOE pin functions as IRQ5 pin. (initial value)
Note: * On use of this pin as TMOE pin, see 7.3.2, Port Mode Register 4 (PMR4).
Bit 4: P14/IRQ4 pin function switch (IRQC4)
Bit 4 IRQC4 0 1 Description P14/IRQ4 pin functions as P14 pin. P14/IRQ4 pin functions as IRQ4 pin. (initial value)
Bit 3: P13/IRQ3 pin function switch (IRQC3)
Bit 3 IRQC3 0 1 Description P13/IRQ3 pin functions as P13 pin. P13/IRQ3 pin functions as IRQ3 pin. (initial value)
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Bit 2: P12/IRQ2 pin function switch (IRQC2)
Bit 2 IRQC2 0 1 Description P12/IRQ2 pin functions as P12 pin. P12/IRQ2 pin functions as IRQ2 pin. (initial value)
Bit 1: P11/IRQ1 pin function switch (IRQC1)
Bit 1 IRQC1 0 1 Description P11/IRQ1 pin functions as P11 pin. P11/IRQ1 pin functions as IRQ1 pin. (initial value)
Bit 0: P10/IRQ0 pin function switch (IRQC0)
Bit 0 IRQC0 0 1 Description P10/IRQ0 pin functions as P10 pin. P10/IRQ0 pin functions as IRQ0 pin. (initial value)
2.
Bit
IRQ edge select register (IEGR)
7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 IEG4 0 R/W 3 -- 1 -- 2 -- 1 -- 1 IEG1 0 R/W 0 IEG0 0 R/W
Initial value Read/Write
IEGR is an 8-bit read/write register, used to designate whether pins IRQ0, IRQ1, and IRQ4 are set to rising edge sensing or falling edge sensing. Bits 7 to 5: Reserved bits Bits 7 to 5 are reserved; they always read 1, and cannot be modified. Bit 4: IRQ4 pin input edge select (IEG4)
Bit 4 IEG4 0 1 Description Falling edge of IRQ4 pin input is detected. Rising edge of IRQ4 pin input is detected. (initial value)
Bits 3 and 2: Reserved bits Bits 3 and 2 are reserved; they always read 1, and cannot be modified.
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Bit 1: IRQ1 pin input edge select (IEG1)
Bit 1 IEG1 0 1 Description Falling edge of IRQ1 pin input is detected. Rising edge of IRQ1 pin input is detected. (initial value)
Bit 0: IRQ0 pin input edge select (IEG0)
Bit 0 IEG0 0 1 Description Falling edge of IRQ0 pin input is detected. Rising edge of IRQ0 pin input is detected. (initial value)
3.
Bit
Interrupt enable register 1 (IENR1)
7 -- 1 -- 6 -- 1 -- 5 IEN5 0 R/W 4 IEN4 0 R/W 3 IEN3 0 R/W 2 IEN2 0 R/W 1 IEN1 0 R/W 0 IEN0 0 R/W
Initial value Read/Write
IENR1 is an 8-bit read/write register for controlling whether external interrupts are enabled or disabled. Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved; they always read 1, and cannot be modified. Bits 5 to 0: IRQ5 to IRQ0 interrupt enable (IEN5 to IEN0)
Bit 5 to 0 IEN5 to IEN0 0 1 Description Disables interrupt requests via IRRI5 to IRRI0. Enables interrupt requests via IRRI5 to IRRI0. (initial value)
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4.
Bit
Interrupt enable register 2 (IENR2)
7 -- 0 R/W 6 -- 0 R/W 5 IENDT 0 R/W 4 IENTE 0 R/W 3 IENTD 0 R/W 2 IENTC 0 R/W 1 IENTB 0 R/W 0 IENTA 0 R/W
Initial value Read/Write
IENR2 is an 8-bit read/write register for controlling whether direct transfer and timer A to E overflow interrupts are enabled or disabled. Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved. Both read and write are possible. Bit 5: Direct transfer interrupt enable (IENDT)
Bit 5 IENDT 0 1 Description Disables interrupt requests (direct transfer) via IRRDT. Enables interrupt requests via IRRDT. (initial value)
Bits 4 to 0: Timer E to A interrupt enable (IENTE to IENTA)
Bits 4 to 0 IENTE to IENTA 0 1 Description Disables interrupt requests via IRRTE to IRRTA. Enables interrupt requests via IRRTE to IRRTA. (initial value)
5.
Bit
Interrupt enable register 3 (IENR3)
7 IENAD 0 R/W 6 IENKS 0 R/W 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 IENS2 0 R/W 0 IENS1 0 R/W
Initial value Read/Write
IENR3 is an 8-bit read/write register for controlling whether interrupts for A/D conversion complete, key scan, and serial communication interface 1 and 2 are enabled or disabled.
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Bit 7: A/D conversion complete interrupt enable (IENAD)
Bit 7 IENAD 0 1 Description Disables interrupt requests via IRRAD. Enables interrupt requests via IRRAD. (initial value)
Bit 6: Key scan interrupt enable (IENKS)
Bit 6 IENKS 0 1 Description Disables interrupt requests via IRRKS. Enables interrupt requests via IRRKS. (initial value)
Bits 5 to 2: Reserved bits Bits 5 to 2 are reserved; they always read 1, and cannot be modified. Bits 1 and 0: Serial communication interface 2 and 1 interrupt enable (IENS2 and IENS1)
Bit 1, 0 IENS2, IENS1 0 1 Description Disables interrupt requests via IRRS2 and IRRS1. Enables interrupt requests via IRRS2 and IRRS1. (initial value)
6.
Bit
Interrupt request register 1 (IRR1)
7 -- 1 -- 6 -- 1 -- 5 IRRI5 0 R/W * 4 IRRI4 0 R/W * 3 IRRI3 0 R/W * 2 IRRI2 0 R/W * 1 IRRI1 0 R/W * 0 IRRI0 0 R/W *
Initial value Read/Write
Note: * Write is enabled only for writing of 0 to clear flag.
IRR1 is an 8-bit read/write register, which is set to 1 when an external interrupt is requested. Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved; they always read 1, and cannot be modified.
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Bits 5 to 0: IRQ5 to IRQ0 interrupt request (IRRI5 to IRRI0)
Bits 5 to 0 IRRI5 to IRRI0 0 1 Description No interrupt request on the corresponding pin (IRQ5 to IRQ0). (initial value)
Setting conditions: When interrupt input is set for the corresponding pin (IRQ5 to IRQ0) by PMR1, and when the edge designated for that pin is input, the corresponding flag (IRRI5 to IRRI0) is set to 1. Clearing method: The flag is not automatically cleared when an interrupt is accepted. Software must be programmed to clear the flag to 0.
7.
Bit
Interrupt request register 2 (IRR2)
7 -- 0 -- 6 -- 0 -- 5 IRRDT 0 R/W * 4 IRRTE 0 R/W * 3 IRRTD 0 R/W * 2 IRRTC 0 R/W* 1 IRRTB 0 R/W * 0 IRRTA 0 R/W *
Initial value Read/Write
Note: * Write is enabled only for writing of 0 to clear flag.
IRR2 is an 8-bit read/write register, which is set to 1 when a direct transfer or Timer A to E overflow interrupt is requested. Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved; they always read 0, and only 0 may be written. Bit 5: Direct transfer interrupt request (IRRDT)
Bits 5 IRRDT 0 1 Description No direct transfer interrupt request. (initial value)
Setting conditions: In subactive mode, when the system control register 2 (SYSCR2) DTON bit = 1, and the system control register 2 (SYSCR2) LSON bit = 0, execution of a SLEEP instruction results in direct transfer to active mode via watch mode. When this happens, a direct transfer interrupt is requested and the IRRDT flag is set to 1. Clearing method: The flag is not automatically cleared when an interrupt is accepted. Software must be programmed to clear the flag to 0.
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Bits 4 to 0: Timers E to A interrupt request (IRRTE to IRRTA)
Bits 4 to 0 IRRTE to IRRTA 0 1 Description No overflow interrupt request on the corresponding timer (E to A). (initial value)
Setting conditions: When a Timer E to A overflow interrupt is requested, the corresponding flag (IRRTE to IRRTA ) is set to 1. Clearing method: The flag is not automatically cleared when an interrupt is accepted. Software must be programmed to clear the flag to 0.
8.
Interrupt request register 3 (IRR3)
Bit Initial value Read/Write 7 IRRAD 0 R/W * 6 IRRKS 0 R/W * 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 IRRS2 0 R/W * 0 IRRS1 0 R/W *
Note: * Write is enabled only for writing of 0 to clear flag.
IRR3 is an 8-bit read/write register, which is set to 1 when an interrupt is requested for A/D conversion complete, key scan, or serial communication interface 2 or 1. Bit 7: A/D conversion complete interrupt request (IRRAD)
Bit 7 IRRAD 0 1 Description No A/D conversion complete interrupt request. (initial value)
Setting conditions: When the A/D converter completes A/D conversion, an interrupt is requested and the IRRAD flag is set to 1. Clearing method: The flag is not automatically cleared when an interrupt is accepted. Software must be programmed to clear the flag to 0.
Bit 6: Key scan interrupt request (IRRKS)
Bit 6 IRRKS 0 1 Description No key scan interrupt request. (initial value)
Setting conditions: When the VFD controller/driver requests an interrupt, the IRRKS flag is set to 1. Clearing method: The flag is not automatically cleared when an interrupt is accepted. Software must be programmed to clear the flag to 0.
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Bits 5 to 2: Reserved bits Bits 5 to 2 are reserved; they always read 1, and cannot be modified. Bits 1 and 0: Serial communication interface 2 and 1 interrupt request (IRRS2, IRRS1)
Bits 1, 0 IRRS2, IRRS1 0 1 Description No transfer complete or error interrupt request by the corresponding serial communication interface. (initial value)
Setting conditions: When an interrupt is requested due to transfer complete or error on serial communication interface 2 or 1, the corresponding flag (IRRS2 or IRRS1) is set to 1. Clearing method: The flag is not automatically cleared when an interrupt is accepted. Software must be programmed to clear the flag to 0.
3.2.4 External Interrupts There are six external interrupts, IRQ5 to IRQ0. These interrupts are requested by means of input signals at pins IRQ5 to IRQ0. Interrupts IRQ4, IRQ1, and IRQ0 are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG4, IEG1, and IEG0 in the IRQ edge select register (IEGR). The other external interrupts, IRQ5, IRQ3, and IRQ2, are detected by falling edge sensing only. In order to validate external interrupt input, it is first necessary to set the corresponding bit in port mode register 1 (PMR1) to 1. When the designated edge is input at pins IRQ5 to IRQ0, the corresponding bit in interrupt request register 1 (IRR1) is set to 1. After the interrupt is accepted, the flag that was set is not automatically cleared, so the interrupt handling routine must be programmed to clear the flag to 0. A given interrupt request may be masked by clearing its interrupt enable flag to 0. Interrupts IRQ5 to IRQ0 are enabled by setting to 1 bits IEN5 to IEN0 in interrupt enable register 1. All interrupts can be masked by setting the I bit in CCR to 1. When an interrupt exception request is received for interrupts IRQ5 to IRQ0 and an interrupt handler is executed, the I bit is set to 1. The order of priority is from IRQ0 (high) to IRQ5 (low). For details see table 3-2. A noise canceller function can be set for IRQ0 interrupts, in which case a noise cancellation circuit double-samples its input every 256 states. If the sampling results do not match, noise is assumed and the request is not accepted.
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3.2.5 Internal Interrupts There are ten internal interrupts that can be raised by the on-chip peripheral modules. These interrupts can be masked by setting the I bit in CCR to 1. When an internal interrupt request is accepted and an interrupt handler is executed, the I bit is set to 1. On the order of priority of interrupts from on-chip peripheral modules, see table 3-2. 3.2.6 Operations When an Interrupt is Raised Interrupts are controlled by an interrupt controller. Figure 3-2 gives a block diagram of this interrupt controller, while figure 3-3 shows the flow up to interrupt acceptance.
Interrupt controller
IRQ 5 to IRQ 0 interrupt request flag or internal interrupt request flag
Priority decision
Interrupt request
IRQ 5 to IRQ 0 interrupt request flag or internal interrupt enable flag
I
CCR (CPU)
Figure 3-2 Block Diagram of Interrupt Controller
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Program execution state Interrupt request occured Yes IRQ0 Yes No IRQ1 Yes No IRQ2 Yes 16 interrupts No No SCI2 Yes A/D Yes No
I=0 Yes PC contents saved
No
Pending
CCR contents saved I1 Branch to interrupt handling routine Notation: PC: Program counter CCR: Condition code register I: I bit of CCR
Figure 3-3 Flow up to Interrupt Acceptance
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The following operations take place when an interrupt is raised. 1. When an interrupt is raised by external interrupt pin input or by a peripheral module, an interrupt request signal is sent to the interrupt controller. When the interrupt controller is sent an interrupt request signal, it sets the interrupt request flag. Of the interrupts for which the corresponding interrupt enable flag is set to 1, that with the highest priority is selected, while the others are masked. (See table 3-2.) The CCR I bit is referenced, and if it is cleared to 0, the highest priority interrupt request is accepted. If the I bit is set to 1, the interrupt request is deferred. If an interrupt request is accepted, then after the presently executing instruction is completed, PC and CCR contents are saved to the stack. The stack state in this case is as shown in figure 3-4. The PC value saved in the stack shows the address of the first instruction to be executed upon return from the interrupt. The CCR I bit is set to 1, masking all other interrupts. A vector address is generated for the accepted interrupt, then the contents of that address are read and sent to PC. When program execution resumes, it starts from this address indicated in PC.
2.
3.
4.
5.
6. 7.
Note: No interrupt detection takes place immediately after completion of ORC, ANDC, XORC, or LDC instructions.
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SP - 4 SP - 3 SP - 2 SP - 1 SP (R7) Stack area
SP (R7) SP + 1 SP + 2 SP + 3 SP + 4
CCR CCR* PCH PCL Even address
Prior to start of interrupt exception handling
Notation: PCH: Upper 8 bits of program counter (PC) PCL: Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer
Contents saved to stack
After completion of interrupt exception handling
Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt. 2. Saving and restoring of register contents must always be done in word size, and must start from an even-numbered address. * Ignored on return from interrupt.
Figure 3-4 Stack State after Completion of Interrupt Exception Handling Figure 3-5 shows a typical interrupt sequence.
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Interrupt is accepted
Interrupt level decision and wait for end of instruction Instruction prefetch Internal processing Stack access Vector fetch Internal processing
Prefetch instruction of interrupt-handling routine
Interrupt request signal
or SUB
Internal address bus (1) (3) (5) (6)
(8)
(9)
Internal read signal
Internal write signal
Figure 3-5 Interrupt Sequence
(2) (4) (1) (7) (9)
Internal data bus (16 bits)
(10)
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(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.) (5) SP - 2 (6) SP - 4 (7) CCR (8) Vector address (9) Starting address of interrupt-handling routine (contents of vector) (10) First instruction of interrupt-handling routine
3.2.7 Return from an Interrupt After completion of interrupt handling, the handler routine ends by executing an RTE instruction, to resume the original program from the point the interrupt. When RTE is executed, the values saved in the stack are restored to CCR and PC as shown in figure 3-6. Instruction execution resumes from the address indicated in PC.
(Processing of RTE instruction)
Memory contents of address indicated in SP are sent to CCR. SP (R7) SP value +2 SP + 1 SP + 2 Memory contents of address indicated in SP are sent to PC. SP + 3 SP + 4 SP value +2 CCR CCR* PC H PC L
(Stack state)
SP - 4 SP - 3
CCR CCR* PC H PC L
Stack SP - 2 area
SP - 1 SP (R7)
Stack area
CCR and PC values restored Before RTE instruction is executed After RTE instruction is executed
Note: Ignored on return from interrupt.
Figure 3-6 Stack State When RTE Instruction is Executed 3.2.8 Interrupt Response Time Table 3-4 shows the number of wait states after an interrupt request flag is set and until the first instruction of the interrupt handler is executed. Table 3-4 Interrupt Wait States
No. 1 2 3 4 5 Item Waiting time for completion of executing instruction* Saving of PC and CCR to stack Vector fetch Instruction fetch Internal processing Total Note: * Not including EEPMOV instruction. States 1 to 13 4 2 4 4 15 to 27
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3.2.9 Valid Interrupts in Each Mode Table 3-5 shows the valid interrupts in each mode. For details of the modes, see 3.3, System Modes. Table 3-5 Valid Interrupts in Each Mode
Mode Interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Key scan Timer A overflow Timer B overflow Timer C overflow Timer D overflow Timer E overflow Direct transfer SCI1 transfer complete, error SCI2 transfer complete, error A/D conversion complete Active

Sleep

Standby

Watch
Subactive
x x x x x x
x x x x x x
x x x x x
x x x x x x x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x
x

Note: The above table does not include interrupts raised during a mode transition. Notation:
:
When an interrupt request flag is set, interrupt exception handling is started if the CCR I bit = 0 and the interrupt enable bit = 1 for that interrupt. In sleep mode, standby mode, and watch mode, mode transition takes place before the interrupt exception handler starts.
: When a SLEEP instruction is executed while the DTON bit = 1 and the LSON bit = 0, the system goes to watch mode and the interrupt request flag is set in synchronization with the subclock. When the interrupt request flag is set, if that interrupt enable flag = 1 and the CCR I bit = 0, the system goes to active mode and the interrupt exception handler starts. x: The interrupt request flag is not set, and no mode transition occurs.
Rev. 3.00, 12/94, page 77 of 334
3.2.10 Notes on Stack Area Use When word data is accessed with the H8/300L Series, the least significant bit of the address is read as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should not indicate an odd address. To avoid this, use PUSH Rn (MOV.W Rn, @-SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. Setting an odd address in SP may cause the CPU to misoperate. An example of this is shown in figure 3-7.
PCH SP PCL
SP
R1L PCL
H'FEFC H'FEFD
SP
H'FEFF
BSR instruction SP-set to H'FEFF
MOV.B R1L, @-R7 Contents of PCH are lost
Stack accessed beyond SP
Notation: PCH: Upper byte of program counter PCL: Lower byte of program counter R1L: General register R1L SP: Stack pointer
Figure 3-7 CPU Operation When Odd Address is Set in SP Word access is also performed when the condition code register (CCR) is saved and restored by the interrupt exception-handling sequence and RTE instruction. When CCR is saved, the CCR value is saved in both the upper and lower bytes of the word data. When CCR is restored, it is loaded with the value at the even address. The value at the odd address is ignored.
Rev. 3.00, 12/94, page 78 of 334
3.3 System Modes
The H8/300L CPU is equipped with power-down modes for minimizing power dissipation. These and the other system modes are described below. There are five modes altogether, as follows. * * * * * Active mode Sleep mode Standby mode Watch mode Subactive mode Low-power operation modes
Figure 3-8 shows the transitions among these modes.
SSBY = 1 and TMA3 = 1 and SLEEP instruction SSBY = 0 and SLEEP instruction Active mode IRQ 0 or IRQ 1 or timer A LSON = 0 and IRQ0 , or LSON = 0 and time base * Watch mode IRQ 0 or IRQ 1 SSBY = 1 and TMA3 = 0 and SLEEP instruction DTON = 0 LSON = 0 and and SLEEP DTON = 1 and instruction LSON = 1 and SLEEP instruction IRQ0, or LSON = 1 and time base* Subactive mode RES RES RES Reset RES RES
Sleep mode
Standby mode
Note: * Time base: Timer A interrupt during time-based operation running on subclock.
Figure 3-8 System Mode Transition Diagram
Rev. 3.00, 12/94, page 79 of 334
3.3.1 Active Mode In active mode, the CPU executes programs in synchronization with the system clock. 3.3.2 Low-Power Operation Mode The H8/300L CPU supports four low-power operation modes, sleep mode, standby mode, watch mode, and subactive mode. These modes are described below. Sleep mode: Sleep mode is entered by executing a SLEEP instruction while the SSBY bit in system control register 1 (SYSCR1) is cleared to 0. As soon as the SLEEP instruction has been executed, the CPU and on-chip peripheral modules halt operation. The contents of the internal registers of the CPU and on-chip peripheral modules, as well as the RAM contents, are retained. Standby mode is entered by executing a SLEEP instruction while the SSBY bit in system control register 1 (SYSCR1) is set to 1 and timer mode register A (TMA) bit TMA3 = 0. In this mode, the CPU, system clock, and on-chip peripheral modules halt all operations. Output from the on-chip peripheral modules is reset; but as long as a minimum required voltage is applied, the contents of the internal registers of the CPU and on-chip peripheral modules, as well as the RAM contents, are retained. Standard I/O ports go to high impedance state, and high-voltage ports go to PMOS buffer off state. Watch mode is entered by executing a SLEEP instruction while the SSBY bit in system control register 1 (SYSCR1) is set to 1 and timer mode register A (TMA) bit TMA3 = 1. In this mode, the CPU, system clock, and on-chip peripheral modules (except for the time base of Timer A) halt all operations. Output from the on-chip peripheral modules is reset; but as long as a minimum required voltage is applied, the contents of the internal registers of the CPU and on-chip peripheral modules, as well as the RAM contents, are retained. Standard I/O ports go to high impedance state, and high-voltage ports go to PMOS buffer off state. Subactive mode is entered when a time base or IRQ0 interrupt request is accepted in watch mode while the LSON bit in system control register 1 (SYSCR1) is set to 1. In this mode the CPU operates in synchronization with the subclock. On-chip peripheral modules other than Timer A halt operation. Output from the on-chip peripheral modules is reset; but as long as a minimum required voltage is applied, the contents of the internal registers of the on-chip peripheral modules are retained. Standard I/O ports go to high impedance state, and high-voltage ports go to PMOS buffer off state.
Standby mode:
Watch mode:
Subactive mode:
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Table 3-6 shows the internal states in each mode. Table 3-6 Internal States in Operation Modes
Function System clock Subclock CPU operation Instruction RAM Register I/O Peripheral module IRQ0 interrupts IRQ1 Timer A Timer B Timer C Timer D Timer E SCI1, SCI2 VFD Active Sleep Standby Watch Halted Functions Halted Retained Retained Subactive Halted Functions Functions Functions Functions
Functions Functions Halted Functions Functions Functions Functions Halted Functions Retained Functions Retained Functions Retained Halted Retained Retained
Retained*1 Retained*1 Functions*1, *2 Functions Retained Retained Functions Retained Retained
Functions Functions Functions Functions Functions Functions Retained
IRQ2 to IRQ5 Functions Retained Functions Retained Functions Retained Functions Retained Functions Retained Functions Retained Functions Retained (output is reset) Functions Retained (output is reset) Functions Retained
Functions Functions Retained Retained Retained Retained Retained Retained Retained (output is reset) Retained (output is reset) Retained
Functions*3 Functions*3 Retained Retained Retained Retained Retained Retained (output is reset) Retained (output is reset) Retained Retained Retained Retained Retained Retained Retained (output is reset) Retained (output is reset) Retained
PWM
A/D
Notes: 1. Register contents retained; output high-impedance. 2. Input (read) functions. 3. Functions when the time base function is selected.
Rev. 3.00, 12/94, page 81 of 334
1.
Sleep mode
Operation in sleep mode is described below. * Transition to sleep mode The system goes from active mode to sleep mode when a SLEEP instruction is executed while the SSBY bit in system control register 1 (SYSCR1) is cleared to 0. In this mode CPU operation is halted but the register, RAM, and port contents are retained. The clock pulse generator operates, as do external interrupts (IRQ1 and IRQ0) and timer A. * Clearing sleep mode Sleep mode is cleared by an interrupt (IRQ1, IRQ0, or timer A) or by input at the RES pin. -- Clearing by interrupt (IRQ1, IRQ0, or timer A) When IRQ1, IRQ0, or timer A interrupt request is raised, sleep mode is cleared and an interrupt exception handler starts processing. When the I bit in the condition code register (CCR) is set to 1 or the particular interrupt is masked by the interrupt enable register, sleep mode is not cleared. Before transition to sleep mode, other interrupts should be disabled. -- Clearing by RES pin When the RES pin goes to low level, the CPU goes to reset state and sleep mode is cleared. 2. Standby mode
Operation in standby mode is described below. * Transition to standby mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in system control register 1 (SYSCR1) is set to 1 and bit TMA3 in timer mode register A (TMA) is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning. As long as a minimum required voltage is applied, the CPU register contents and data in the on-chip RAM will be retained. Standard I/O ports go to high impedance state, and high-voltage ports go to PMOS buffer off state.
Rev. 3.00, 12/94, page 82 of 334
*
Clearing standby mode Standby mode is cleared by an external interrupt (IRQ1, IRQ0) or by input at the RES pin. -- Clearing by interrupt (IRQ1, IRQ0) When an IRQ1, IRQ0 interrupt signal is input, the clock pulse generator starts. After the time set in bits STS2-STS0 in system control register 1 (SYSCR1) has elapsed, a stable clock signal is supplied to the LSI as a whole, standby mode is cleared, and the interrupt exception handler starts processing. Before the system goes to standby mode, other interrupts should be disabled. When the I bit in the condition code register (CCR) is set to 1 or the particular interrupt is masked by the interrupt enable register, standby mode is not cleared. -- Clearing by RES pin When the RES pin goes to low level, the clock pulse generator starts and standby mode is cleared. After the time for stabilizing of pulse generator output has elapsed, when the RES pin is switched to high level the CPU starts processing the exception handler. Since clock signals are supplied to the entire LSI at the same time as the clock pulse generator starts functioning, the RES pin should be kept at low level until the pulse generator output stabilizes.
3.
Watch mode
Operation in watch mode is described below. * Transition to watch mode The system goes from active mode to watch mode when a SLEEP instruction is executed while the SSBY bit in system control register 1 (SYSCR1) is set to 1 and bit TMA3 in timer mode register A (TMA) is set to 1. From subactive mode, watch mode is entered when a SLEEP instruction is executed while the DTON bit in system control register 2 (SYSCR2) is cleared to 0. In watch mode, operation of the system clock pulse generator and of on-chip peripheral modules (except timer A time base) is halted. Output from the on-chip peripheral modules is reset; but as long as a minimum required voltage is applied, the contents of the internal registers of the CPU and on-chip peripheral modules, and the on-chip RAM contents, are retained.
Rev. 3.00, 12/94, page 83 of 334
*
Clearing watch mode Watch mode is cleared by timer A clock function interrupt (time base), by an IRQ0 interrupt, or by input at the RES pin. -- Clearing by timer A time base interrupt or IRQ0 interrupt When timer A overflow occurs or an IRQ0 interrupt signal is input, if the LSON bit in system control register 1 (SYSCR1) is cleared to 0, the clock pulse generator starts. After the time set in bits STS2-STS0 in system control register 1 (SYSCR1) has elapsed, a stable clock signal is supplied to the LSI as a whole, watch mode is cleared, and the interrupt exception handler starts processing. If LSON = 1, the system goes to subactive mode. In watch mode, the clock signal is divided into a subclock (SUB), which is supplied to timer A. Timer A then switches to time base operation. Before the system goes to watch mode, other external interrupts should be disabled. When the I bit in the condition code register (CCR) is set to 1 or the particular interrupt is masked by the interrupt enable register, watch mode is not cleared. -- Clearing by RES pin When the RES pin goes to low level, the clock pulse generator starts and watch mode is cleared. After the time for stabilizing of pulse generator output has elapsed, when the RES pin is switched to high level the CPU starts processing the exception handler. Since clock signals are supplied to the entire LSI at the same time as the clock pulse generator starts functioning, the RES pin should be kept at low level until the pulse generator output stabilizes.
4.
Subactive mode Operation in subactive mode is described below.
*
Transition to subactive mode Subactive mode is entered from watch mode when the LSON bit in system control register 1 (SYSCR1) is set to 1 at the time of a timer A time base interrupt or IRQ0 interrupt request. In subactive mode, the CPU operates in synchronization with the subclock (SUB). The onchip peripheral modules (except for timer A time base) halt operation. Output from the onchip peripheral modules is reset; but as long as a minimum required voltage is applied, the contents of the internal registers of the on-chip peripheral modules are retained. Standard I/O ports go to high impedance state, and high-voltage ports go to PMOS buffer off state.
Rev. 3.00, 12/94, page 84 of 334
*
Clearing subactive mode Subactive mode is cleared by a SLEEP instruction or by input at the RES pin. -- Clearing by SLEEP instruction When a SLEEP instruction is executed in subactive mode, the subactive mode is cleared. If the DTON bit of system control register 2 (SYSCR2) is cleared to 0 at the time the SLEEP instruction is executed, the system goes to watch mode. If DTON = 1 and LSON = 0, then when a direct transfer interrupt request is raised the clock pulse generator starts operation. After the time set in bits STS2-STS0 in system control register 1 (SYSCR1) has elapsed, a stable clock signal is supplied to the LSI as a whole, and the system goes to active mode. Before the system goes to active mode, other interrupts should be disabled. When the I bit in the condition code register (CCR) is set to 1 or the direct transfer interrupt is masked in the interrupt enable register, direct transfer from subactive mode to active mode does not take place. -- Clearing by RES pin When the RES pin goes to low level, the clock pulse generator starts and subactive mode is cleared. After the time for stabilizing of pulse generator output has elapsed, when the RES pin is switched to high level the CPU starts processing the exception handler. Since clock signals are supplied to the entire LSI at the same time as the clock pulse generator starts functioning, the RES pin should be kept at low level until the pulse generator output stabilizes.
Rev. 3.00, 12/94, page 85 of 334
3.3.3 Application Notes 1. In order to ensure sufficient time for the clock pulse generator to reach stable operation after clearing of standby mode or watch mode, or after direct transfer from subactive to active mode, bits STS2-STS0 in system control register 1 (SYSCR1) should be set as follows. When a ceramic oscillator is used Set bits STS2-STS0 for a waiting time of at least 10 ms (see figure 3-9). For details, see 3.4.1, System Control Register 1 (SYSCR1). * When an external clock is used Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set.
*
Oscillator wave V
t
Waiting time 10 ms Oscillator stabilization time tr Power on or standby cleared
Figure 3-9 Waiting time 2. Transition from subactive mode to active mode should be made when the LSON bit in SYSCR1 is cleared to 0 and the DTON bit in system control register 2 (SYSCR2) is set to 1. Direct transfer is not possible when LSON bit = 1.
Rev. 3.00, 12/94, page 86 of 334
3.4 System Control Registers
Table 3-7 shows how the system control registers (SYSCR1 and SYSCR2) are configured. These two registers are used to control the power-down modes. Table 3-7 Register Configuration
Name System control register 1 System control register 2 Abbreviation SYSCR1 SYSCR2 R/W R/W R/W Initial Value H'00 H'F4 Address H'FFF0 H'FFF1
3.4.1 System Control Register 1 (SYSCR1)
Bit Initial value Read/Write 7 SSBY 0 R/W * 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 LSON 0 R/W 2 -- 0 R/W 1 -- 0 -- 0 -- 0 --
Note: * Write is enabled only in active mode.
SYSCR1 is an 8-bit read/write register for control of power-down modes. Bit 7: Standby (SSBY) This bit designates transition to standby mode. When standby mode is cleared by an external interrupt and the system goes to active mode, this bit remains set to 1. It must be cleared by writing a 0. Writing is possible only in active mode.
Bit 7 SSBY 0 1 Explanation When a SLEEP instruction is executed transition from active mode to sleep mode occures. (initial value)
When a SLEEP instruction is executed transition from active mode to standby mode or watch mode occures.
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Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0) When a mode in which the system clock is stopped (standby, watch, or subactive mode) is cleared, the time the system waits for stable clock operation is set in these bits. Designation should be made as per the table below, based on the operating frequency, for a wait time of at least 10 ms.
Bit 6 STS2 0 0 0 0 1 Bit 5 STS1 0 0 1 1 * Bit 4 STS0 0 1 0 1 * Explanation Wait time = 8,192 states. (initial value)
Wait time = 16,384 states. Wait time = 32,768 states. Wait time = 65,536 states. Wait time = 131,072 states.
Note: * Don't care.
Bit 3: Low speed on flag (LSON) This bit chooses the system clock () or subclock (SUB) as the CPU operating clock when watch mode is cleared. Since this relates to the transitions between operation modes, functioning is based on the combination of other control bits and interrupt input.
Bit 3 LSON 0 1 Explanation The CPU operates on the system clock (). The CPU operates on the subclock (SUB). (initial value)
Bit 2: Reserved bit This bit is reserved. Both read and write are possible. Bits 1 and 0: Reserved bits These bits are reserved; they are always read as 0, and cannot be modified.
Rev. 3.00, 12/94, page 88 of 334
3.4.2 System Control Register 2 (SYSCR2)
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 DTON 0 W* 2 -- 1 -- 1 -- 0 R/W 0 -- 0 R/W
Note: * Write is enabled only in subactive mode.
SYSCR2 is an 8-bit read/write register for control of direct transfer from subactive mode to active mode. Bits 7 to 4: Reserved bits These bits are reserved; they are always read as 1, and cannot be modified. Bit 3: Direct transfer on flag (DTON) This bit designates whether transition is made to active mode or to watch mode when a SLEEP instruction is executed in subactive mode. When transfer to active mode is designated, the transition takes place via watch mode to allow time for the clock pulse generator to achieve stable operation.
Bit 3 DTON 0 1 Explanation When a SLEEP instruction is executed in subactive mode, the system goes to watch mode. (initial value)
When a SLEEP instruction is executed in subactive mode while the LSON bit in system control register 1 (SYSCR1) is cleared to 0, a direct transfer interrupt request is raised, the system goes to active mode via watch mode, and the interrupt exception handler is processed.
Bit 2: Reserved bit This bit is reserved; it is always reads as 1, and cannot be modified. Bits 1 and 0: Reserved bits These bits are reserved. Both read and write are possible.
Rev. 3.00, 12/94, page 89 of 334
Rev. 3.00, 12/94, page 90 of 334
Section 4 ROM
4.1 Overview
The H8/3724 and H8/3754 Series LSIs are equipped with a mask ROM or electrically programmable ROM (PROM) on chip. ROM capacity is 24 kbytes for the H8/3723 and H8/3753, 32 kbytes for the H8/3724 and H8/3754, 40 kbytes for the H8/3725, and 48 kbytes for the H8/3726. The ROM is connected to the CPU by means of a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. The H8/3724ZTATTM version has a 32-kbyte PROM, and the H8/3726ZTATTM version has a 48-kbyte PROM. 4.1.1 Block Diagram Figure 4-1 gives a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits) Internal data bus (lower 8 bits)
H'0000 H'0002
H'0001 H'0003
*
Even-numbered addresses
*
Odd-numbered addresses
Note: * The last address differs as follows depending on the ROM size. Even-Numbered Address H8/3723 H8/3753 H8/3724 H8/3754 H8/3725 H8/3726 H'5FFE H'7DFE H'9FFE H'BFFE Odd-Numbered Address H'5FFF H'7DFF H'9FFF H'BFFF
Figure 4-1 ROM Block Diagram
Rev. 3.00, 12/94, page 91 of 334
4.2 PROM Mode
4.2.1 Setting to PROM Mode If the on-chip ROM is a PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as an ordinary EPROM. The H8/3724ZTATTM is programmed in the same way as the HN27C256H EPROM, while the H8/3726ZTATTM is programmed like the HN27C101. Table 4-1 shows how to set the chip to PROM mode. Table 4-1 Setting to PROM Mode
Pin Name Test pin TEST Mode pin MD0 (P40/FS16) Mode pin MD1 (P41/FS17) Mode pin MD2 (P17/Vdisp) High level Setting High level Low level
4.2.2 Socket Adapter Pin Arrangement and Memory Map A standard PROM programmer is used to program the PROM, along with a socket adapter for conversion to 28 or 32 pins as shown in table 4-2. Figure 4-2 shows pin correspondence of the socket adapter. The memory map is shown in figure 4-3. Table 4-2 Socket Adapter
Product H8/3724ZTATTM Package 80-pin (FP-80A) 80-pin (FP-80B) H8/3726ZTATTM 80-pin (FP-80A) 80-pin (FP-80B) Socket Adapter HS3724ESH01H HS3724ESF01H HS3726ESH01H HS3726ESF01H
Rev. 3.00, 12/94, page 92 of 334
H8/3724ZTATTM
FP-80A 10 64 65 66 67 68 69 70 71 30 31 32 33 34 35 36 37 47 17 49 50 51 52 53 54 48 26 27 38 28 29 55, 74 7, 3 4, 6 8 FP-80B 12 66 67 68 69 70 71 72 73 32 33 34 35 36 37 38 39 49 19 51 52 53 54 55 56 50 28 29 40 30 31 57, 76 9, 5 6, 8 10 Pin RES P90 P91 P92 P93 P94 P95 P96 P97 P50 P51 P52 P53 P54 P55 P56 P57 P70 P16 P72 P73 P74 P75 P76 P77 P71 P43 P42 P17 P41 P40 VCC, AVCC VSS, AVSS TEST, X1 OSC1
EPROM Socket
Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 CE OE VCC VCC VCC VSS VSS VCC VSS VCC VSS HN27C256H 1 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 20 22 28 28 28 14 14 28 14 28 16
Note: Pins not indicated above should be left open.
Figure 4-2 Socket Adapter Pin Correspondence (1)
Rev. 3.00, 12/94, page 93 of 334
H8/3726ZTATTM
FP-80A 10 64 65 66 67 68 69 70 71 30 31 32 33 34 35 36 37 47 17 49 50 51 52 53 23 22 24 54 48 26 27 38 28 29 55, 74 7, 3 4, 6 8 FP-80B 12 66 67 68 69 70 71 72 73 32 33 34 35 36 37 38 39 49 19 51 52 53 54 55 25 24 26 56 50 28 29 40 30 31 57, 76 9, 5 6, 8 10 Pin RES P90 P91 P92 P93 P94 P95 P96 P97 P50 P51 P52 P53 P54 P55 P56 P57 P70 P16 P72 P73 P74 P75 P76 P46 P47 P45 P77 P71 P43 P42 P17 P41 P40 VCC, AVCC VSS, AVSS TEST, X1 OSC1
EPROM Socket
Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 PGM CE OE VCC VCC VCC VSS VSS VCC VSS VCC VSS HN27C101 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 31 22 24 32 32 32 16 16 32 16 32 16
Note: Pins not indicated above should be left open.
Figure 4-2 Socket Adapter Pin Correspondence (2)
Rev. 3.00, 12/94, page 94 of 334
Address in MCU mode H'0000
Address in PROM mode H'0000
H'5FFF
H'5FFF
H'7DFF (1) H8/3724 Memory Map
H'7DFF
Address in MCU mode H'0000
Address in PROM mode H'0000
H'5FFF
H'5FFF
H'7DFF
H'7DFF
H'9FFF
H'9FFF
H'BFFF (2) H8/3726 Memory Map
H'BFFF
Figure 4-3 Memory Map in PROM Mode
Rev. 3.00, 12/94, page 95 of 334
4.3 H8/3724ZTAT Programming
The write, verify, and other sub-modes of PROM mode are selected as shown in table 4-3. Table 4-3 Sub-Mode Selection in PROM Mode (H8/3724ZTAT)
Pin Mode Write Verify Programming disabled Notation: L: Low level H: High level VPP: VPP level VCC: VCC level CE L H H OE H L H VPP VPP VPP VPP VCC VCC VCC VCC EO7 to EO0 Data input Data output High impedance EA14 to EA0 Address input Address input Address input
The specifications for writing and reading the on-chip PROM are identical to those for the HN27C256H standard EPROM. 4.3.1 Writing and Verifying An efficient, high-speed programming method is provided for writing and verifying the PROM data. This method achieves high speed without any increase in voltage stress on the device and without lowering the reliability of written data. H'FF data is written in unused address areas. The basic flow of this high-speed programming method is shown in figure 4-4. Table 4-4 and table 4-5 give the electrical characteristics in programming mode, while the timing chart is given in figure 4-5.
Rev. 3.00, 12/94, page 96 of 334
Start Select write or verify mode VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V Address = 0
n=0 n + 1 n Yes No n < 25 Write with t PW = 1 ms 5% No Go
Verify Go Write with t OPW = 3n ms No
Address + 1 address
Last address? Yes VCC
Select read mode = 5.0 V 0.5 V, VPP = VCC 0.6 V
Error
No Go
Read all addresses Go End
Figure 4-4 High-Speed Programming Flowchart (H8/3724)
Rev. 3.00, 12/94, page 97 of 334
Table 4-4 DC Characteristics (H8/3724) (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Input highlevel voltage Input lowlevel voltage Output highlevel voltage Output lowlevel voltage EA14 to EA0, OE, CE EA14 to EA0, OE, CE EO7 to EO0 EO7 to EO0 Symbol Min VIH VIL VOH VOL 2.4 -0.3 2.4 -- -- -- -- Typ Max -- -- -- -- -- -- -- Test Unit Conditions
VCC + 0.3 V 0.8 -- 0.45 2 40 40 V V V A mA mA IOH = -200 A IOL = 1.6 mA VIN = 5.25 V/0.5 V
Input leakage EO7 to EO0, EA14 to EA0, |ILI| current OE, CE VCC current VPP current ICC IPP
Table 4-5 AC Characteristics (H8/3724) (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)
Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Programming pulse width CE pulse width for overwrite programming VCC setup time Data output delay time Symbol tAS tOES tDS tAH tDH tDF tVPS tPW tOPW tVCS tOE Min 2 2 2 0 2 0 2 0.95 2.85 2 0 Typ -- -- -- -- -- -- -- 1.0 -- -- -- Max -- -- -- -- -- 130 -- 1.05 78.75 -- 500 Unit s s s s s ns s ms ms s ns Test Conditions Figure 4-5*
Notes: * Input pulse level: 0.8 to 2.2 V Input rise time/fall time 20 ns Timing reference levels Input: 1.0 V, 2.0 V Output: 0.8 V, 2.0 V
Rev. 3.00, 12/94, page 98 of 334
Write Address t AS Data t DS VPP VPP VCC VCC GND t VPS Input data t DH
Verify
t AH Output data t DF
VCC
t VCS
CE t PW t OPW t OES t OE
OE
Figure 4-5 PROM Write/Verify Timing (H8/3724) 4.3.2 Precautions When Writing 1. Use the specified voltage and timing for writing. The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage than this can permanently damage the LSI. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C256H specifications will result in a correct VPP of 12.5 V. 2. Make sure the index marks on the PROM programmer socket, socket adapter, and the LSI pins are properly aligned so as to avoid excessive current flow to the LSI. Before writing, be sure the LSI is properly mounted in the socket adapter and PROM programmer. Avoid touching the socket adapter or LSI during programming. A contact fault may occur, resulting in write error.
Rev. 3.00, 12/94, page 99 of 334
3.
4.4 H8/3726ZTAT Programming
The write, verify, and other sub-modes of PROM mode are selected as shown in table 4-6. Table 4-6 Sub-Mode Selection in PROM Mode (H8/3726ZTAT)
Pin Mode Write Verify Programming disabled CE L L L L H H Notation: L: Low level H: High level VPP: VPP level VCC: VCC level OE H L L H L H PGM L H L H L H VPP VPP VPP VPP VCC VCC VCC VCC O7 to O0 Data input Data output High impedance A16 to A0 Address input Address input Address input
The specifications for writing and reading the on-chip PROM are identical to those for the HN27C101 standard EPROM. Do not set to page programming mode, however, since this mode is not supported. 4.4.1 Writing and Verifying An efficient, high-performance programming method is provided for writing and verifying the PROM data. This method achieves high speed without any increase in voltage stress on the device and without lowering the reliability of written data. H'FF data is written in unused address areas. Figure 4-6 shows the basic flow of this high-performance programming method. Table 4-7 and table 4-8 give the electrical characteristics in programming mode, while the timing chart is given in figure 4-7.
Rev. 3.00, 12/94, page 100 of 334
Start Select write or verify mode VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V Address = 0
n=0 n + 1 n Yes No n < 25 No Write tPW = 0.2 ms 5%
Verify Go Write t OPW = 0.2n ms No
Address + 1 address
Last address? Yes VCC
Select read mode = 5.0 V 0.5 V, VPP = VCC 0.6 V
Error
No
Read all addresses Go End
Figure 4-6 High-Speed Programming Flowchart (H8/3726)
Rev. 3.00, 12/94, page 101 of 334
(Provisional specifications) Table 4-7 DC Characteristics (H8/3726) (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Symbol Min Typ 2.4 -- Max Unit Test Conditions Input high-level EO7 to EOo, EA16 to VIH voltage EA0, OE, CE, PGM Input low-level voltage Output highlevel voltage Output lowlevel voltage Input leakage current VCC current VPP current EO7 to EOo, EA16 to VIL EA0, OE, CE, PGM EO7 to EO0 EO7 to EO0 VOH VOL VCC + 0.3 V 0.8 -- 0.45 2 40 40 V V V A mA mA IOH = -200 A IOL = 1.6 mA Vin = 5.25 V/0.5 V
-0.3 -- 2.4 -- -- -- -- -- -- -- -- --
EO7 to EOo, EA16 to ILI EA0, OE, CE, PGM ICC IPP
Table 4-8 AC Characteristics (H8/3726) (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)
Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Programming pulse width OE pulse width for overwrite programming VCC setup time CE setup time Data output delay time Symbol tAS tOES tDS tAH tDH tDF tVPS tPW tOPW tVCS tCES tOE Min 2 2 2 0 2 0 2 0.19 0.19 2 2 0 Typ -- -- -- -- -- -- -- 0.20 -- -- -- -- Max -- -- -- -- -- 130 -- 0.21 5.25 -- -- 150 Unit s s s s s ns s ms ms s s ns Test Conditions See figure 4-7*
Note: Input pulse level: 0.8 V to 2.2 V Input rise/fall time 20 ns Timing reference levels Input: 1.0 V, 2.0 V Output: 0.8 V, 2.0 V Rev. 3.00, 12/94, page 102 of 334
Write Address t AS Data t DS VPP VPP VCC VCC +1 VCC t VPS Input data t DH
Verify
t AH Output data t DF
VCC
t VCS
CE t CES PGM t PW t OES t OE
OE
Figure 4-7 PROM Write and Verify Timing (H8/3726) 4.4.2 Precautions When Writing 1. Use the specified voltage and timing for writing. The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage than this can permanently damage the LSI. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C101 will result in a correct VPP of 12.5 V. 2. Make sure the index marks on the PROM programmer socket, socket adapter, and the LSI pins are properly aligned so as to avoid excessive current flow to the LSI. Before writing, be sure the LSI is properly mounted in the socket adapter and PROM programmer.
Rev. 3.00, 12/94, page 103 of 334
3.
Avoid touching the socket adapter or LSI during programming. A contact fault may occur, resulting in write error. Do not set page programming mode, since this mode is not supported. H8/3726 has a PROM size of 48 kbytes. When programming, write H'FF to addresses H'C000 to H'1FFFF.
4. 5.
4.5 Reliability of Written Data
An effective way to assure the data holding characteristics of the programmed chips is to bake them at 150C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 4-8 shows a flowchart of this screening procedure.
Write program and verify written data
Bake chips with power off 150C 10C, 48 Hr +8 Hr * -0 Hr
Read and check program V CC = 4.5 V, 5.5 V
Install
Note: * Baking time is measured from when the oven reaches 150C.
Figure 4-8 Recommended Screening Procedure If write errors occur repeatedly while the same PROM programmer is being used, stop the programming and check for problems in the PROM programmer and socket adapter, etc. In case problems appear in checking the program after writing and screening, please contact your Hitachi representative.
Rev. 3.00, 12/94, page 104 of 334
Section 5 RAM
5.1 Overview
The H8/3724 and H8/3754 Series LSIs are equipped with a high-speed static RAM on chip. RAM capacity is 384 bytes for the H8/3723, 512 bytes for the H8/3724, 640 bytes for the H8/3725, and 1,024 bytes for the H8/3726, H8/3753, and H8/3754. 5.1.1 Block Diagram Figure 5-1 gives a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits) Internal data bus (lower 8 bits)
*
*
H'FE7C H'FE7E Even-numbered addresses
H'FE7D H'FE7F Odd-numbered addresses
Note: * The first address differs as follows depending on the RAM size. Even-Numbered Address H8/3723 H8/3724 H8/3725 H8/3726 H8/3753 H8/3754 H'FE00 H'FD80 H'FD00 H'FB80 Odd-Numbered Address H'FE01 H'FD81 H'FD01 H'FB81
Figure 5-1 RAM Block Diagram
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5.1.2 Display RAM Area The H8/3724 and H8/3754 Series assigns RAM addresses H'FEC0 to H'FEFF for use as a display RAM for a VFD controller/driver. If no VFD controller/driver is used, this area is available as an ordinary RAM.
Rev. 3.00, 12/94, page 106 of 334
Section 6 Clock Pulse Generators
6.1 Overview
Clock oscillator circuitry (CPG: Clock Pulse Generator) is provided on chip. These circuits consist of a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, system clock divider, and prescaler S for use by on-chip peripheral modules. The subclock pulse generator consists of a subclock oscillator, subclock divider, and prescaler W for time-base use. 6.1.1 Block Diagram Figure 6-1 gives a block diagram of the clock pulse generators.
System clock pulse generator
Prescaler S OSC1 OSC2 System clock oscillator f OSC System clock divider (1/2)
/2 to /8192
Prescaler W X1 X2 Subclock oscillator fX Subclock divider (1/8)
SUB /32 SUB
Subclock pulse generator
Figure 6-1 Block Diagram of Clock Pulse Generators
Rev. 3.00, 12/94, page 107 of 334
6.2 System Clock Generator
A clock pulse signal is supplied to the system clock divider either by connecting to a crystal or ceramic oscillator, or by connecting to an external clock input. 1. * Connecting to a crystal oscillator Circuit configuration Figure 6-2 shows a typical method for connecting to a crystal oscillator.
C1 OSC 1 OSC 2 Rf C2 Rf = 1 M 20% C1 = C 2 = 12 pF 20%
Figure 6-2 Typical Connection to Crystal Oscillator * Crystal oscillator Figure 6-3 shows the equivalent circuit of a crystal oscillator. An oscillator having the characteristics given in table 6-1 should be used.
CL L OSC 1 RS OSC 2
C0
Figure 6-3 Equivalent Circuit of Crystal Oscillator Table 6-1 Crystal Oscillator Parameters
Frequency (MHz) 2 Rs max () Co max (pF) 500 7 4 100 7 8 50 7
Rev. 3.00, 12/94, page 108 of 334
2. *
Connecting to a ceramic oscillator Circuit configuration
Figure 6-4 shows a typical method for connecting to a ceramic oscillator.
C1 Ceramic oscillator Rf
OSC 1
C2 R f : 1 M 20% C 1 : 30 pF 20% C 2 : 30 pF 20%
OSC 2
Figure 6-4 Typical Connection to a Ceramic Oscillator 3. Notes on board design When generating a clock pulse by connecting the LSI to a crystal or ceramic oscillator, pay careful attention to the following points. Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (See figure 6-5.) The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2.
Rev. 3.00, 12/94, page 109 of 334
To be avoided
Signal A Signal B H8/3724 Series
C2 OSC 1
OSC 2 C1
Figure 6-5 Board Design of Oscillator Circuit 4. * External clock input Circuit configuration When an external clock is used, it is input at pin OSC1. Pin OSC2 should be left open. Figure 6-6 shows a typical connection.
OSC 1 Open
External clock input
OSC 2
Figure 6-6 External Clock Input (example) * External clock
Twice clock frequency () 45% to 55%
Frequency Duty
Rev. 3.00, 12/94, page 110 of 334
6.3 Subclock Generator
1. Connecting to 32.768 kHz crystal oscillator A clock pulse signal is supplied to the subclock divider by connecting to a 32.768 kHz crystal oscillator, as shown in figure 6-7. The precautions here are the same as those noted above for the system clock.
C1 X1 X2 C2 C1 = C2 = 15 pF typ
Figure 6-7 Typical Connection to Crystal Oscillator (subclock) Figure 6-8 shows the equivalent circuit of a crystal oscillator.
L
CS
RS
C0 C0 = 1.5 pF typ RS = 14 k typ f = 32.768 kHz
Figure 6-8 Equivalent Circuit of Crystal Oscillator 2. Pin connection when not using subclock When no subclock is used, connect VCC to pin X1 and leave pin X2 open, as shown in figure 6-9.
Rev. 3.00, 12/94, page 111 of 334
VCC X1 X2 Open
Figure 6-9 Pin Connection When Not Using Subclock
6.4 Note on Oscillators
Oscillator characteristics of both the masked ROM and ZTATTM versions are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the oscillator element manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding its maximum rating.
Rev. 3.00, 12/94, page 112 of 334
Section 7 I/O Ports
7.1 Overview
The H8/3724 and H8/3754 Series are provided with seven 8-bit I/O ports* (of which four are high-voltage ports), one 4-bit I/O port (high-voltage port), one 2-bit I/O port, and one 8-bit input port. Table 7-1 indicates the functions of each port. Port 0 is standard input port. Ports 1, 8, 9, and A are standard I/O ports, consisting of a port control register (PCR) that controls input and output, and a port data register (PDR) for storing output data. Input or output can be assigned to individual bits. Ports 3, 4, 5, 6, and 7 are high-voltage ports, able to handle an impressed voltage of up to VCC - 40 V. Input and output are controlled in individual bits, by reading from and writing to PDR. Note: * Pin P17 of port 1 is a high-voltage input-only pin, while pin P16 is a standard input-only pin. Reading a port gives the following results. * Reading a general-purpose port -- Reading a general-purpose port while PCR = 0 gives the pin level. -- Reading a general-purpose port while PCR = 1 gives the value of the corresponding PDR bit. -- Reading a pin assigned to an on-chip peripheral function gives the pin level. * Reading a high-voltage port -- Reading a pin assigned to a general-purpose port gives the pin level. -- Reading a pin assigned to digit output or segment output use gives the value of the corresponding PDR bit.
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Table 1 Port Functions
Port Port 0 Port 1 Description 8-bit standard input port Pin P17: 1-bit high-voltage input port Pin P16: 1-bit standard input port Pins P15 to P10: 6-bit standard I/O port Pins P07 to P00/ AN7 to AN0 P17/Vdisp P16/EVENT P15/IRQ5/ TMOE Other Functions Analog data input channels 7 to 0 Power source for VFD driver Timer D event input External interrupt 5; Timer E output Function Switching Register PMR0 Mask option PMR1 PMR1 PMR4 PMR1 VFSR VFSR VFSR DBR VFSR VFDR VFDR --
External interrupts 4 to 0 P14 to P10 IRQ4 to IRQ0 Port 3 Port 4 Port 5 Port 6 4-bit high-voltage I/O port 8-bit high-voltage I/O port 8-bit high-voltage I/O port 8-bit high-voltage I/O port P33 to P30/ VFD segment pins 27 to 24 FS27 to FS24 P47 to P40/ VFD segment pins 23 to 16 FS23 to FS16 P57 to P50/ FS15 to FS8 P67 to P60/ FD7 to FD0/ FS0 to FS7 P77 to P70/ FS15 to FS8 P87 to P80 P97/UD P96/SO2 P95/SI2/CS P94/SCK2 P93/SO1 P92/SI1 P91/SCK1 P90/PWM Port A 2-bit standard I/O port PA1, PA0 VFD segment pins 15 to 8 VFD digit pins 7 to 0/segment pins 0 to 7 VFD digit pins 15 to 8 None
Port 7 Port 8 Port 9
8-bit high-voltage I/O port 8-bit standard I/O port 8-bit standard I/O port
Timer C count-up/down setting PMR2 Serial communication interface PMR3 2 data output Serial communication interface 2 data input/chip select output Serial communication interface 2 clock I/O Serial communication interface 1 data output Serial communication interface 1 data input Serial communication interface 1 clock I/O 14-bit PWM waveform output pin None --
Note: Port 2 is for future expansion, and is not included on 80-pin versions. Rev. 3.00, 12/94, page 114 of 334
7.1.1 Port Types and Mask Options The choice of I/O pin options and the resulting states are shown in table 7-2. Upon reset, registers PDR, PCR, and PMR are initialized, cancelling the choices of peripheral functions. When the chip goes to a low-power mode, the on-chip peripheral function input gates are always on; so unless input levels are fixed there will be an increase in dissipated current. Table 7-2 Choice of I/O Port Options
For Standard I/O Pins Class I/O pins Pins P15 to P10, P87 to P80, P97 to P90, PA1, PA0 P16 SCK2, SCK1 (output mode) SO2, SO1, PWM, TMOE SCK2, SCK1 (input mode) SI2, SI1, IRQ5 to IRQ0, UD, EVENT With Pull-Up MOS (Type B) With pull-up MOS No Pull-Up MOS (Type C) No pull-up MOS
Input-only pins On-chip peripheral function I/O pins On-chip peripheral function output pins On-chip peripheral function input pins
With pull-up MOS With pull-up MOS With pull-up MOS With pull-up MOS
No pull-up MOS No pull-up MOS No pull-up MOS No pull-up MOS
Note: If external clock input mode is selected while the serial communication interface is being used, pins SCK2 and SCK1 will be input-only pins. For High-Voltage Pins No Pull-Down Resistor (Type D) No pull-down resistor With Pull-Down Resistor (Type E) With pull-down resistor. Source side of pull-down resistor connects to Vdisp power source. Vdisp power source With pull-down resistor. Source side of pull-down resistor connects to Vdisp power source. Rev. 3.00, 12/94, page 115 of 334
Class I/O pins
Pins P33 to P30, P47 to P40, P57 to P50, P67 to P60, P77 to P70 P17
Input-only pins
No pull-down resistor
On-chip peripheral FS27 to FS0, No pull-down resistor function output pins FD15 to FD0
Table 7-3 shows the mask options with mask ROM versions. A mask ROM version is compatible with a ZTATTM version only when C and D options are selected for all pins. Table 7-3 Correspondence between Mask ROM and ZTATTM Versions
Type Mask ROM ZTAT B Option -- C Option Fixed D Option Fixed E Option --
Application Notes 1. When circuit type E, "with pull-down resistor," is chosen, the source side of the pull-down resistor is connected to a Vdisp power source. Accordingly, the mask option making pin P17/Vdisp a Vdisp power source must also be chosen. 2. Type C, "no pull-up MOS," is the only option available for port 0.
7.1.2 Pull-Up MOS Ports 1*, 8, 9, and A, which are standard input/output ports, can be designated by mask option as with pull-up MOS or without pull-up MOS (CMOS) (does not apply to ZTATTM versions). Figure 7-1 shows the pull-up MOS circuit configuration. When "with pull-up MOS" is selected by mask option, the pull-up MOS will always be on, regardless of the port data register (PDR) and port control register (PCR) settings. (See table 7-4.) Note: * Pin P17/Vdisp is a high-voltage pin, so the pull-up MOS option cannot be selected for this pin.
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STBY *2 VCC
*1
VCC
Pull-up MOS PDR PCR
CMOS buffer
VSS Input data
Notes: 1. Dotted lines indicate mask option. 2. In low-power modes (except sleep mode), the pull-up MOS is switched off by a STBY signal.
Figure 7-1 Pull-up MOS Circuit Configuration Table 7-4 Pull-up MOS Control
Mask Option PCR PDR CMOS buffer PMOS NMOS Pull-up MOS 0 Off Off On With Pull-Up MOS (type B) 0 1 Off Off On 0 Off On On 1 1 On Off On 0 Off Off -- No Pull-Up MOS (type C) 0 1 Off Off -- 0 Off On -- 1 1 On Off --
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7.1.3 Pull-Down Resistor Ports 3, 4, 5, 6, and 7, which are high-voltage I/O ports, can be designated by mask option as with pull-down resistor or without pull-down resistor (PMOS open drain output) (does not apply to ZTATTM versions). Figure 7-2 shows the pull-down resistor circuit configuration. When the "with pull-down resistor" option is chosen, the source side of the pull-down resistor is connected to a Vdisp power source. Accordingly, the mask option making pin P17/Vdisp a Vdisp power source must also be chosen.
VCC
STBY
PDR
*
Vdisp
Input control Input data
Note: * Dotted lines indicate mask option.
Figure 7-2 Pull-down Resistor Circuit Configuration
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7.2 Port 0
7.2.1 Overview Port 0 is an 8-bit standard input-only port. Figure 7-3 shows the pin configuration.
P0 7 /AN 7 (input) P0 6 /AN 6 (input) P0 5 /AN 5 (input) Port 0 P0 4 /AN 4 (input) P0 3 /AN 3 (input) P0 2 /AN 2 (input) P0 1 /AN 1 (input) P0 0 /AN 0 (input)
Figure 7-3 Port 0 Pin Configuration 7.2.2 Register Configuration and Description Table 7-5 shows the port 0 register configuration. Table 7-5 Port 0 Registers
Name Port mode register 0 Port data register 0 Abbrev. PMR0 PDR0 R/W W R Initial Value H'00 -- Address H'FFEF H'FFD0
1.
Bit
Port mode register 0 (PMR0)
7 AN7 0 W 6 AN6 0 W 5 AN5 0 W 4 AN4 0 W 3 AN3 0 W 2 AN2 0 W 1 AN1 0 W 0 AN0 0 W
Initial value Read/Write
Each PMR0 bit designates whether the corresponding port 0 pin is to be used as a general input port or as an analog input channel to the A/D converter. Upon reset, PMR0 is initialized to H'00.
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Bit n ANn 0 1
Explanation Pin P0n/ANn is a general input port. Pin P0n/ANn is an analog input channel. (n = 0 to 7) (initial value)
2.
Bit
Port data register 0 (PDR0)
7 PDR0 7 -- R 6 PDR0 6 -- R 5 PDR0 5 -- R 4 PDR0 4 -- R 3 PDR03 -- R 2 PDR0 2 -- R 1 PDR0 1 -- R 0 PDR0 0 -- R
Initial value Read/Write
When the corresponding bit in PMR0 is 0, the pin state can be read from PDR0. If the corresponding PMR0 bit is 1, PDR0 is read as 1. 7.2.3 Pin Functions Table 7-6 gives the port 0 pin functions. Table 7-6 Port 0 Pin Functions
Pin P07/AN7 to P00/AN0 Selection Method and Pin Functions Functions are switched as follows by means of bits AN7 to AN0 in PMR0. ANn Pin function 0 P0n input pin 1 ANn input pin
7.2.4 Pin States Table 7-7 shows the port 0 pin states in each operating mode. Table 7-7 Port 0 Pin States
Pins P07/AN7 to P00/AN0 Reset High impedance Sleep Contents retained Standby High impedance Watch High impedance Subactive High impedance Active Normal operation
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7.3 Port 1
7.3.1 Overview Port 1 consists of a 6-bit standard I/O port, a 1-bit standard input-only port, and a 1-bit highvoltage input-only port. Figure 7-4 shows the pin configuration.
P17 /Vdisp P16 /EVENT
(high-voltage input/power source) (input/input)
P15 /IRQ5 /TMOE (IO/input/output) Port 1 P14 /IRQ4 P13 /IRQ3 P12 /IRQ2 P11 /IRQ1 P10 /IRQ0 Note: IO indicates input/output. (IO/input) (IO/input) (IO/input) (IO/input) (IO/input)
Figure 7-4 Port 1 Pin Configuration 7.3.2 Register Configuration and Description Table 7-8 shows the port 1 register configuration. Table 7-8 Port 1 Registers
Name Port mode register 1 Port control register 1 Port data register 1 Port mode register 4 Abbrev. PMR1 PCR1 PDR1 PMR4 R/W R/W W R/W R/W Initial Value H'00 H'C0 Not fixed H'0F Address H'FFEB H'FFE1 H'FFD1 H'FFEE
1.
Bit
Port mode register 1 (PMR1)
7
NOISE CANCEL
6 EVENT 0 R/W
5 IRQC5 0 R/W
4 IRQC4 0 R/W
3 IRQC3 0 R/W
2 IRQC2 0 R/W
1 IRQC1 0 R/W
0 IRQC0 0 R/W
Initial value Read/Write
0 R/W
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PMR1 is an 8-bit read/write register, controlling the selection of pin functions for pin P16/EVENT and pins P15/IRQ5 through P10/IRQ0, and used also to turn the pin IRQ0 noise cancellation function on and off. Upon reset, PMR1 is initialized to H'00. Note: Before switching pin functions using bits IRQ5 to IRQ0 in PMR1, first set the interrupt enable flag to disable interrupts. After the pin functions have been switched, issue any instruction before clearing the interrupt request flag to 0. For details see section 3.2.3 1, Port mode register (PMR1).
Bit 7: Noise cancel (NOISE CANCEL) This bit turns the pin IRQ0 noise canceller function on and off. In standby, watch, and subactive modes the noise canceller function is off regardless of this bit's setting.
Bit 7 NOISE CANCEL 0 1 Explanation Noise canceller function is off. (initial value)
Noise canceller function is on. Input is double-sampled at intervals of 256 states. If the input values do not match, noise is assumed.
Bit 6: P16/EVENT pin function switch (EVENT) This bit selects whether pin P16/EVENT is used as P16 pin or as EVENT pin.
Bit 6 EVENT 0 1 Explanation P16/EVENT pin functions as P16 pin.* P16/EVENT pin functions as EVENT pin (timer D event input). (initial value)
Note: * Even when pin P16/EVENT is used as P16 pin, it is possible to have the timer D counter incremented when pin P16 is read. When timer D is used in this way, the counter must be cleared by means of the CLR bit in timer mode register D (TMD).
Bit 5: P15/IRQ5/TMOE pin function switch (IRQC5) This bit selects whether pin P15/IRQ5/TMOE is used as P15/TMOE pin or as IRQ5 pin.
Bit 5 IRQC5 0 1 Explanation P15/IRQ5/TMOE pin functions as P15/TMOE pin. P15/IRQ5/TMOE pin functions as IRQ5 input pin. (initial value)
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Bit 4: P14/IRQ4 pin function switch (IRQC4) This bit selects whether pin P14/IRQ4 is used as P14 pin or as IRQ4 pin.
Bit 4 IRQC4 0 1 Explanation P14/IRQ4 pin functions as P14 pin. P14/IRQ4 pin functions as IRQ4* input pin. (initial value)
Note: * Rising or falling edge sensing can be designated for pin IRQ4. For details see 3.2.3 2, IRQ edge select register (IEGR).
Bit 3: P13/IRQ3 pin function switch (IRQC3) This bit selects whether pin P13/IRQ3 is used as P13 pin or as IRQ3 pin.
Bit 3 IRQC3 0 1 Explanation P13/IRQ3 pin functions as P13 pin. P13/IRQ3 pin functions as IRQ3 input pin. (initial value)
Bit 2: P12/IRQ2 pin function switch (IRQC2) This bit selects whether pin P12/IRQ2 is used as P12 pin or as IRQ2 pin.
Bit 2 IRQC2 0 1 Explanation P12/IRQ2 pin functions as P12 pin. P12/IRQ2 pin functions as IRQ2 input pin. (initial value)
Bit 1: P11/IRQ1 pin function switch (IRQC1) This bit selects whether pin P11/IRQ1 is used as P11 pin or as IRQ1 pin.
Bit 1 IRQC1 0 1 Explanation P11/IRQ1 pin functions as P11 pin. P11/IRQ1 pin functions as IRQ1* input pin. (initial value)
Note: * Rising or falling edge sensing can be designated for pin IRQ1. For details see 3.2.3 2, IRQ edge select register (IEGR).
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Bit 0: P10/IRQ0 pin function switch (IRQC0) This bit selects whether pin P10/IRQ0 is used as P10 pin or as IRQ0 pin.
Bit 0 IRQC0 0 1 Explanation P10/IRQ0 pin functions as P10 pin. P10/IRQ0 pin functions as IRQ0* input pin. (initial value)
Note: * Rising or falling edge sensing can be designated for pin IRQ0. For details see 3.2.3 2, IRQ edge select register (IEGR).
2.
Bit
Port control register 1 (PCR1)
7 -- 1 -- 6 -- 1 -- 5 PCR15 0 W 4 PCR14 0 W 3 PCR13 0 W 2 PCR12 0 W 1 PCR11 0 W 0 PCR10 0 W
Initial value Read/Write
PCR1 is an 8-bit register for controlling whether each of port 1 pins P15 to P10 functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin from P15 through P10 an output pin, while clearing the bit to 0 makes it an input pin. PCR1 is a write-only register. All bits are read as 1. Bits 7 and 6 are reserved; they always read as 1, and cannot be modified. The settings in PCR1 and in PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I/O pin. Upon reset, PCR1 is initialized to H'00. 3. Port data register 1 (PDR1)
Bit Initial value Read/Write 7 -- --* -- 6 -- --* -- 5 PDR1 5 0 R/W 4 PDR14 0 R/W 3 PDR13 0 R/W 2 PDR1 2 0 R/W 1 PDR11 0 R/W 0 PDR10 0 R/W
Note: * Pins P17 and P16 are for input only; reading PDR1 always gives the level of these pins.
PDR1 is an 8-bit register for storing data of pins P15 through P10. When port 1 is read while PCR1 is set to 1, the PDR1 values will be read directly, without any influence of the pin states. When port 1 is read while PCR1 is cleared to 0, the pin states will be read.
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4.
Bit
Port mode register 4 (PMR4)
7 TEO 0 R/W 6 TEO ON 0 R/W 5 FREQ 0 R/W 4 VRFR 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Initial value Read/Write
PMR4 is an 8-bit read/write register for switching of the P15/IRQ5/TMOE pin function and for controlling the TMOE pin waveform output. Bits 3 to 0 are reserved; they are always read as 1, and cannot be modified. Upon reset, PMR4 is initialized to H'0F. Bit 7: Timer E output function select (TEO) Bit 6: Timer E output on/off (TEO ON) Bit 5: Fixed frequency select (FREQ) Bit 4: Random frequency select (VRFR) The P15/IRQ5/TMOE pin functions are switched as follows, by means of bits 7 to 4 of PMR4 and bit IRQC5 of PMR1.
PMR1 PMR4 Bit 4 VRFR 0 * * 0 Pin Function P15 pin P15 pin Description Pin State Standard I/O port (initial value) Standard I/O port
Bit 5 Bit 7 Bit 6 Bit 5 IRQC5 TEO TEO ON FREQ 0 0 0 0 0 0 1 1 0 * 0 1 0 * * 0
TMOE output pin (off) Low level output TMOE output pin (on) Fixed frequency output: (/2048) 1.95 kHz ( = 4 MHz) 0.98 kHz ( = 2 MHz) TMOE output pin (on) Fixed frequency output: (/1024) 3.9 kHz ( = 4 MHz) 1.95 kHz ( = 2 MHz) TMOE output pin (on) Random frequency output: Toggle output indicating Timer E overflow IRQ5 input pin External interrupt request input
0
1
1
1
0
0
1
1
*
1
1
*
*
*
*
Note: * Don't care
Rev. 3.00, 12/94, page 125 of 334
7.3.3 Pin Functions Table 7-9 shows the port 1 pin functions. Table 7-9 Port 1 Pin Functions
Pin P17/Vdisp Selection Method and Pin Function Selected by mask option P17 high-voltage input pin P16/EVENT Power source for VFD driving (Vdisp)
Function switched as follows by EVENT bit in PMR1 EVENT Pin function 0 P16 input pin 1 EVENT input pin*
Note: Timer D event input P15/IRQ5/TMOE, P14/IRQ4 to P10/IRQ0 Function switched as follows by bits IRQC5 to IRQC0* in PMR1 and bit n in PCR1 PMR1 PCR1n Pin function 0 0 1 1 -- IRQn input pin
P1n input pin P1n output pin
Notes: 1. Before switching pin functions using bits IRQC5 to IRQC0 in PMR1, first set the interrupt enable flag to disable interrupts. After the pin functions have been switched, issue any instruction before clearing the interrupt request flag to 0. For details see section 3.2.3 1, Port mode register (PMR1). 2. Before entering power-down mode, if there are pins set to external interrupt input by bits IRQC5 to IRQC0 in PMR1, these should be kept from floating by external connection or should be set to general I/O ports in PMR1 prior to state transition. 3. For details on the TMOE function, refer to section 7.3.2 4, Port mode register 4 (PMR4). IRQ4, IRQ1, and IRQ0 input can be set for either rising edge or falling edge detection by register IEGR. For details, refer to section 3.2.3 2, IRQ edge select register (IEGR). IRQ0 and IRQ1 can be used as event input pins for timer B and timer C, respectively. For details, refer to section 8, Timers.
Rev. 3.00, 12/94, page 126 of 334
7.3.4 Pin States Table 7-10 shows the port 1 pin states in each operating mode. Table 7-10 Port 1 Pin States
Pins P17/Vdisp Reset High impedance or Vdisp High impedance or pulled up Sleep Standby Watch High impedance or Vdisp High impedance Subactive High impedance or Vdisp High impedance Active Normal operation or Vdisp Normal operation
High High impedance impedance or Vdisp or Vdisp Contents retained High impedance
P16/EVENT, P15/IRQ5/ TMOE, P14/IRQ4 to P10/IRQ0
Rev. 3.00, 12/94, page 127 of 334
7.4 Port 3
7.4.1 Overview Port 3 is a 4-bit high-voltage I/O port. Figure 7-5 shows the pin configuration.
P3 3 /FS27 (IO/output) Port 3 P3 2 /FS26 (IO/output) P3 1 /FS25 (IO/output) P3 0 /FS24 (IO/output) Note: IO indicates input/output.
Figure 7-5 Port 3 Pin Configuration 7.4.2 Register Configuration and Description Table 7-11 shows the port 3 register configuration. Table 7-11 Port 3 Registers
Name Port data register 3 Abbrev. PDR3 R/W R/W Initial Value H'F0 Address H'FFD3
1.
Bit
Port data register 3 (PDR3)
7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PDR3 3 0 R/W 2 PDR3 2 0 R/W 1 PDR3 1 0 R/W 0 PDR3 0 0 R/W
Initial value Read/Write
PDR3 is an 8-bit register for storing the data of port 3 pins P33 to P30. Bits 7 to 4 are reserved; they are always read as 1, and cannot be modified. Upon reset, PDR3 is initialized to H'F0.
Rev. 3.00, 12/94, page 128 of 334
7.4.3 Pin Functions Table 7-12 shows the port 3 pin functions. Table 7-12 Port 3 Pin Functions
Pin P33/FS27 to P30/FS24 Selection Method and Pin Function After designation of the segment pins to be used, in bits SR4-SR0 of the VFD segment control register (VFSR), bit VFDE in the digit beginning register (DBR) is set to 1 and VFD controller/driver operation is started. During key scan intervals, pins designated for segment output can also be manipulated by the CPU as general-purpose ports. Even while the VFD controller is operating, it is possible to switch segment pins to general ports by writing 0 in the VFLAG bit of VFSR. VFLAG Pin function 0 Pins P33 to P30 are all general I/O pins. 1 Pins designated by bits SR4-SR0 are segment output pins.* Other pins are for general I/O.
Note: * When a pin functioning as a segment output pin is read, the value of the corresponding bit in PDR3 is read.
7.4.4 Pin States Table 7-13 shows the port 3 pin states in each operating mode. Table 7-13 Port 3 Pin States
Pins P33/FS27 to P30/FS24 Reset Sleep Standby Watch Subactive Active
High Contents impedance or retained pulled down
High High High Normal impedance or impedance or impedance or operation pulled down pulled down pulled down
Rev. 3.00, 12/94, page 129 of 334
7.5 Port 4
7.5.1 Overview Port 4 is an 8-bit high-voltage I/O port. Figure 7-6 shows the pin configuration.
P47 /FS 23 (IO/output) P46 /FS 22 (IO/output) P45 /FS 21 (IO/output) Port 4 P44 /FS 20 (IO/output) P43 /FS 19 (IO/output) P42 /FS 18 (IO/output) P41 /FS 17 (IO/output) P40 /FS 16 (IO/output)
Note: IO indicates input/output.
Figure 7-6 Port 4 Pin Configuration 7.5.2 Register Configuration and Description Table 7-14 shows the port 4 register configuration. Table 7-14 Port 4 Registers
Name Port data register 4 Abbrev. PDR4 R/W R/W Initial Value H'00 Address H'FFD4
1.
Bit
Port data register 4 (PDR4)
7 PDR4 7 0 R/W 6 PDR4 6 0 R/W 5 PDR4 5 0 R/W 4 PDR44 0 R/W 3 PDR4 3 0 R/W 2 PDR4 2 0 R/W 1 PDR4 1 0 R/W 0 PDR4 0 0 R/W
Initial value Read/Write
PDR4 is an 8-bit register for storing the data of port 4 pins P47 to P40. Upon reset, PDR4 is initialized to H'00.
Rev. 3.00, 12/94, page 130 of 334
7.5.3 Pin Functions Table 7-15 shows the port 4 pin functions. Table 7-15 Port 4 Pin Functions
Pin P47/FS23 to P40/FS16 Selection Method and Pin Function After designation of the segment pins to be used, in bits SR4-SR0 of the VFD segment control register (VFSR), bit VFDE in the digit beginning register (DBR) is set to 1 and VFD controller/driver operation is started. During key scan intervals, pins designated for segment output can also be manipulated by the CPU as general-purpose ports. Even while the VFD controller/driver is operating, it is possible to switch segment pins to general-purpose ports by writing 0 in the VFLAG bit of VFSR. VFLAG Pin function 0 Pins P47 to P40 are all general-purpose I/O pins. 1 Pins designated by bits SR4-SR0 are segment output pins.* Other pins are for general I/O.
Note: * When a pin functioning as a segment output pin is read, the value of the corresponding bit in PDR4 is read.
7.5.4 Pin States Table 7-16 shows the port 4 pin states in each operating mode. Table 7-16 Port 4 Pin States
Pins P47/FS23 to P40/FS16 Reset Sleep Standby Watch Subactive Active
High Contents impedance or retained pulled down
High High High Normal impedance or impedance or impedance or operation pulled down pulled down pulled down
Rev. 3.00, 12/94, page 131 of 334
7.6 Port 5
7.6.1 Overview Port 5 is an 8-bit high-voltage I/O port. Figure 7-7 shows the pin configuration.
P57 /FS8 (IO/output) P56 /FS9 (IO/output) P55 /FS10 (IO/output) Port 5 P54 /FS11 (IO/output) P53 /FS12 (IO/output) P52 /FS13 (IO/output) P51 /FS14 (IO/output) P50 /FS15 (IO/output)
Note: IO indicates input/output.
Figure 7-7 Port 5 Pin Configuration 7.6.2 Register Configuration and Description Table 7-17 shows the port 5 register configuration. Table 7-17 Port 5 Registers
Name Port data register 5 Bit Initial value Read/Write 7 PDR5 7 0 R/W Abbrev. PDR5 6 PDR5 6 0 R/W R/W R/W 5 PDR5 5 0 R/W Initial Value H'00 4 PDR54 0 R/W 3 PDR5 3 0 R/W Address H'FFD5 2 PDR5 2 0 R/W 1 PDR5 1 0 R/W 0 PDR5 0 0 R/W
1.
Port data register 5 (PDR5)
PDR5 is an 8-bit register for storing the data of port 5 pins P57 to P50. Upon reset, PDR5 is initialized to H'00.
Rev. 3.00, 12/94, page 132 of 334
7.6.3 Pin Functions Table 7-18 shows the port 5 pin functions. Table 7-18 Port 5 Pin Functions
Pin P57/FS8 to P50/FS15 Selection Method and Pin Function After designation of the segment pins to be used, in bits SR4-SR0 of the VFD segment control register (VFSR), bit VFDE in the digit beginning register (DBR) is set to 1 and VFD controller/driver operation is started. During key scan intervals, pins designated for segment output can also be manipulated by the CPU as general-purpose ports. Even while the VFD controller/driver is operating, it is possible to switch segment pins to general-purpose ports by writing 0 in the VFLAG bit of VFSR. VFLAG Pin function 0 Pins P57 to P50 are all general-purpose I/O pins. 1 Pins designated by bits SR4-SR0 are segment output pins.* Other pins are for general I/O.
Note: * When a pin functioning as a segment output pin is read, the value of the corresponding bit in PDR5 is read.
7.6.4 Pin States Table 7-19 shows the port 5 pin states in each operating mode. Table 7-19 Port 5 Pin States
Pins P57/FS8 to P50/FS15 Reset Sleep Standby Watch Subactive Active
High Contents impedance or retained pulled down
High High High Normal impedance or impedance or impedance or operation pulled down pulled down pulled down
Rev. 3.00, 12/94, page 133 of 334
7.7 Port 6
7.7.1 Overview Port 6 is an 8-bit high-voltage I/O port. Figure 7-8 shows the pin configuration.
P6 7 /FD7 /FS0 (IO/output/output) P6 6 /FD6 /FS1 (IO/output/output) P6 5 /FD5 /FS2 (IO/output/output) Port 6 P6 4 /FD4 /FS3 (IO/output/output) P6 3 /FD3 /FS4 (IO/output/output) P6 2 /FD2 /FS5 (IO/output/output) P6 1 /FD1 /FS6 (IO/output/output) P6 0 /FD0 /FS7 (IO/output/output)
Note: IO indicates input/output.
Figure 7-8 Port 6 Pin Configuration 7.7.2 Register Configuration and Description Table 7-20 shows the port 6 register configuration. Table 7-20 Port 6 Registers
Name Port data register 6 Bit Initial value Read/Write 7 PDR6 7 0 R/W Abbrev. PDR6 6 PDR6 6 0 R/W R/W R/W 5 PDR6 5 0 R/W Initial Value H'00 4 PDR64 0 R/W 3 PDR6 3 0 R/W Address H'FFD6 2 PDR6 2 0 R/W 1 PDR6 1 0 R/W 0 PDR6 0 0 R/W
1.
Port data register 6 (PDR6)
PDR6 is an 8-bit register for storing the data of port 6 pins P67 to P60. Upon reset, PDR6 is initialized to H'00.
Rev. 3.00, 12/94, page 134 of 334
7.7.3 Pin Functions Table 7-21 shows the port 6 pin functions. Table 7-21 Port 6 Pin Functions
Pin P67/FD7/FS0 to P60/FD0/FS7 Selection Method and Pin Function After designation of the digit pins and segment pins to be used, in bits DR3- DR0 of the VFD digit control register (VFDR), bits SR4-SR0 of the VFD segment control register (VFSR), and bits DBR3-DBR0 of the digit beginning register (DBR), bit VFDE in DBR is set to 1 and VFD controller/driver operation is started. During key scan intervals, pins designated for digit or segment output can also be manipulated by the CPU as general-purpose ports. Even while the VFD controller/driver is operating, it is possible to switch digit pins or segment pins to general-purpose ports by writing 0 in the VFLAG bit of VFSR. VFLAG Pin function 0 Pins P67 to P60 are all general-purpose I/O pins. 1 Pins are designated as digit output pins,* segment output pins,* or general I/O pins by bits DR3-DR0, SR4-SR0, and DBR3-DBR0.
Note: * When a pin functioning as a digit output pin or segment output pin is read, the value of the corresponding bit in PDR6 is read.
7.7.4 Pin States Table 7-22 shows the port 6 pin states in each operating mode. Table 7-22 Port 6 Pin States
Pins P67/FD7/ FS0 to P60/FD0/ FS7 Reset Sleep Standby Watch Subactive Active
High Contents impedance or retained pulled down
High High High Normal impedance or impedance or impedance or operation pulled down pulled down pulled down
Rev. 3.00, 12/94, page 135 of 334
7.8 Port 7
7.8.1 Overview Port 7 is an 8-bit high-voltage I/O port. Figure 7-9 shows the pin configuration.
P77 /FD15 (IO/output) P76 /FD14 (IO/output) P75 /FD13 (IO/output) Port 7 P74 /FD12 (IO/output) P73 /FD11 (IO/output) P72 /FD10 (IO/output) P71 /FD9 (IO/output) P70 /FD8 (IO/output)
Note: IO indicates input/output.
Figure 7-9 Port 7 Pin Configuration 7.8.2 Register Configuration and Description Table 7-23 shows the port 7 register configuration. Table 7-23 Port 7 Registers
Name Port data register 7 Bit Initial value Read/Write 7 PDR7 7 0 R/W Abbrev. PDR7 6 PDR7 6 0 R/W R/W R/W 5 PDR7 5 0 R/W Initial Value H'00 4 PDR74 0 R/W 3 PDR7 3 0 R/W Address H'FFD7 2 PDR7 2 0 R/W 1 PDR7 1 0 R/W 0 PDR7 0 0 R/W
1.
Port data register 7 (PDR7)
PDR7 is an 8-bit register for storing the data of port 7 pins P77 to P70. Upon reset, PDR7 is initialized to H'00.
Rev. 3.00, 12/94, page 136 of 334
7.8.3 Pin Functions Table 7-24 shows the port 7 pin functions. Table 7-24 Port 7 Pin Functions
Pin P77/FD15 to P70/FD8 Selection Method and Pin Function After designation of the digit pins to be used, in bits DR3-DR0 of the VFD digit control register (VFDR), bit VFDE in the digit beginning register (DBR) is set to 1 and VFD controller/driver operation is started. Even while the VFD controller/driver is operating, it is possible to switch digit pins to generalpurpose ports by writing 0 in the VFLAG bit of VFSR. VFLAG Pin function 0 Pins P77 to P70 are all general-purpose I/O pins. 1 Pins designated by bits DR3-DR0 are digit output pins.* Other pins are for general I/O.
Note: * When a pin functioning as a digit output pin is read, the value of the corresponding bit in PDR7 is read.
7.8.4 Pin States Table 7-25 shows the port 7 pin states in each operating mode. Table 7-25 Port 7 Pin States
Pins P77/FD15 to P70/FD8 Reset Sleep Standby Watch Subactive Active
High Contents impedance or retained pulled down
High High High Normal impedance or impedance or impedance or operation pulled down pulled down pulled down
Rev. 3.00, 12/94, page 137 of 334
7.9 Port 8
7.9.1 Overview Port 8 is an 8-bit standard I/O port. Figure 7-10 shows the pin configuration.
P87 (I/O) P86 (I/O) P85 (I/O) Port 8 P84 (I/O) P83 (I/O) P82 (I/O) P81 (I/O) P80 (I/O)
Figure 7-10 Port 8 Pin Configuration 7.9.2 Register Configuration and Description Table 7-26 shows the port 8 register configuration. Table 7-26 Port 8 Registers
Name Port control register 8 Port data register 8 Abbrev. PCR8 PDR8 R/W W R/W Initial Value H'00 H'00 Address H'FFE8 H'FFD8
Rev. 3.00, 12/94, page 138 of 334
1.
Bit
Port control register 8 (PCR8)
7 PCR8 7 0 W 6 PCR8 6 0 W 5 PCR85 0 W 4 PCR84 0 W 3 PCR83 0 W 2 PCR82 0 W 1 PCR81 0 W 0 PCR80 0 W
Initial value Read/Write
PCR8 is an 8-bit register for controlling whether each of port 8 pins P87 to P80 functions as an input or output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes it an input pin. PCR8 is a write-only register. All bits are read as 1. Upon reset, PCR8 is initialized to H'00. 2.
Bit Initial value Read/Write
Port data register 8 (PDR8)
7 PDR8 7 0 R/W 6 PDR8 6 0 R/W 5 PDR8 5 0 R/W 4 PDR84 0 R/W 3 PDR8 3 0 R/W 2 PDR8 2 0 R/W 1 PDR8 1 0 R/W 0 PDR8 0 0 R/W
PDR8 is an 8-bit register for storing the data of port 8 pins P87 to P80. When port 8 is read while PCR8 is set to 1, the PDR8 values will be read directly, without any influence of the pin states. When port 8 is read while PCR8 is cleared to 0, the pin states will be read. Upon reset, PDR8 is initialized to H'00.
Rev. 3.00, 12/94, page 139 of 334
7.9.3 Pin Functions Table 7-27 gives the port 8 pin functions. Table 7-27 Port 8 Pin Functions
Pin P87 to P80 Selection Method and Pin Function Functions are switched as follows by means of the PCR8 bits. PCR8n Pin function 0 P8n input pin 1 P8n output pin
7.9.4 Pin States Table 7-28 shows the port 8 pin states in each operating mode. Table 7-28 Port 8 Pin States
Pins P87 to P80 Reset Sleep Standby High impedance Watch High impedance Subactive High impedance Active Normal operation
High Contents impedance or retained pulled up
Rev. 3.00, 12/94, page 140 of 334
7.10 Port 9
7.10.1 Overview Port 9 is an 8-bit standard I/O port. Figure 7-11 shows the pin configuration.
P97 /UD P96 /SO 2
(IO/input) (IO/output)
P95 /SI 2 /CS (IO/input/output) Port 9 P94 /SCK 2 (IO/IO) P93 /SO1 P92 /SI1 P91 /SCK1 P90 /PWM (IO/output) (IO/input) (IO/IO) (IO/output)
Note: IO indicates input/output.
Figure 7-11 Port 9 Pin Configuration 7.10.2 Register Configuration and Description Table 7-29 shows the port 9 register configuration. Table 7-29 Port 9 Registers
Name Port mode register 2 Port control register 9 Port data register 9 Abbrev. PMR2 PCR9 PDR9 R/W R/W W R/W Initial Value H'00 H'00 H'00 Address H'FFEC H'FFE9 H'FFD9
1.
Bit
Port mode register 2 (PMR2)
7
UP/ DOWN
6 SO2 0 R/W
5 SI2 0 R/W
4 SCK2 0 R/W
3 SO1 0 R/W
2 SI1 0 R/W
1 SCK1 0 R/W
0 PWM 0 R/W
Initial value Read/Write
0 R/W
PMR2 is an 8-bit read/write register, controlling the selection of port 9 pin functions. Upon reset, PMR2 is initialized to H'00.
Rev. 3.00, 12/94, page 141 of 334
Bit 7: P97/UD pin function switch (UP/DOWN) This bit selects whether pin P97/UD is used as a general-purpose I/O port or for Timer C up/down control by UD pin input. This bit is valid only when bit TMC6 = 1 in timer mode register C (TMC) and the pin is being used for up/down control.
Bit 7 UP/DOWN 0 1 Description P97/UD pin functions as P97 I/O pin. (initial value)
P97/UD pin functions as UD input pin. When bit TMC6 in TMC is set to 1, then if the UD pin is high level, timer C is used for count-down, and if UD is low level, timer C is used for count-up.
Bit 6: P96/SO2 pin function switch (SO2) This bit selects whether pin P96/SO2 functions as P96 I/O pin or as SO2 output pin.
Bit 6 SO2 0 1 Description P96/SO2 pin functions as P96 I/O pin. P96/SO2 pin functions as SO2 output pin. (initial value)
Bit 5: P95/SI2/CS pin function switch (SI2) This bit selects whether pin P95/SI2/CS functions as P95 I/O pin or as SI2 input/CS output pin. On switching between SI2 input and CS output see 11.2.5, Port Mode Register 3 (PMR3).
Bit 5 SI2 0 1 Description P95/SI2/CS pin functions as P95 I/O pin. P95/SI2/CS pin functions as SI2 input/CS output pin. (initial value)
Bit 4: P94/SCK2 pin function switch (SCK2) This bit selects whether pin P94/SCK2 functions as P94 I/O pin or as SCK2 I/O pin.
Bit 4 SCK2 0 1 Description P94/SCK2 pin functions as P94 I/O pin. (initial value)
P94/SCK2 pin functions as SCK2 I/O pin. The clock input/output direction and the divider ratio are set in serial mode register 2 (SMR2).
Rev. 3.00, 12/94, page 142 of 334
Bit 3: P93/SO1 pin function switch (SO1) This bit selects whether pin P93/SO1 functions as P93 I/O pin or as SO1 output pin.
Bit 3 SO1 0 1 Description P93/SO1 pin functions as P93 I/O pin. P93/SO1 pin functions as SO1 output pin. (initial value)
Bit 2: P92/SI1 pin function switch (SI1) This bit selects whether pin P92/SI1 functions as P92 I/O pin or as SI1 input pin.
Bit 2 SI1 0 1 Description P92/SI1 pin functions as P92 I/O pin. P92/SI1 pin functions as SI1 input pin. (initial value)
Bit 1: P91/SCK1 pin function switch (SCK1) This bit selects whether pin P91/SCK1 functions as P94 I/O pin or as SCK1 I/O pin.
Bit 1 SCK1 0 1 Description P91/SCK1 pin functions as P91 I/O pin. (initial value)
P91/SCK1 pin functions as SCK1 I/O pin. The clock input/output direction and the divider ratio are set in serial mode register 1 (SMR1).
Bit 0: P90/PWM pin function switch (PWM) This bit selects whether pin P90/PWM pin functions as P90 I/O pin or as PWM output pin.
Bit 0 PWM 0 1 Description P90/PWM pin functions as P90 I/O pin. P90/PWM pin functions as PWM output pin. (initial value)
Rev. 3.00, 12/94, page 143 of 334
2.
Bit
Port control register 9 (PCR9)
7 PCR9 7 0 W 6 PCR9 6 0 W 5 PCR95 0 W 4 PCR94 0 W 3 PCR93 0 W 2 PCR92 0 W 1 PCR91 0 W 0 PCR90 0 W
Initial value Read/Write
PCR9 is an 8-bit register for controlling whether each of port 9 pins P97 to P90 functions as an input or output pin. Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes it an input pin. The settings in PCR9 and PDR9 are valid when the affected pin is designated in PMR2 as a general-purpose I/O pin. PCR9 is a write-only register. All bits are read as 1. Upon reset, PCR9 is initialized to H'00. 3.
Bit Initial value Read/Write
Port data register 9 (PDR9)
7 PDR9 7 0 R/W 6 PDR9 6 0 R/W 5 PDR9 5 0 R/W 4 PDR94 0 R/W 3 PDR9 3 0 R/W 2 PDR9 2 0 R/W 1 PDR9 1 0 R/W 0 PDR9 0 0 R/W
PDR9 is an 8-bit register for storing the data of port 9 pins P97 to P90. When port 9 is read while PCR9 is set to 1, the PDR9 values will be read directly, without any influence of the pin states. When port 9 is read while PCR9 is cleared to 0, the pin states will be read. Upon reset, PDR9 is initialized to H'00.
Rev. 3.00, 12/94, page 144 of 334
7.10.3 Pin Functions Table 7-30 shows the port 9 pin functions. Table 7-30 Port 9 Pin Functions
Pin P97/UD Selection Method and Pin Function Functions are switched as follows by means of the UP/DOWN bit* in PMR2 and bit PCR97 in PCR9. UP/DOWN PCR97 Pin function 0 0 1 1 -- UD input pin
P97 input pin P97 output pin
Note: * Before entering power-down mode, if this pin is set to UD input pin by the UP/DOWN bit in PMR2, it should be kept from floating by external connection or should be set to general I/O use by clearing the UP/DOWN bit to 0 prior to state transition. P96/SO2* Functions are switched as follows by means of bit SO2 in PMR2 and bit PCR96 in PCR9. SO2 PCR96 Pin function 0 0 1 1 -- SO2 output pin
P96 input pin P96 output pin
Note: * PMOS on/off can be controlled for the P96/SO2 pin by means of the SO2PMOS bit in PMR3. For details see 11.2.5, Port Mode Register 3 (PMR3). P95/SI2/ CS Functions are switched as follows by means of bit SI2 in PMR2,* bit CS in PMR3, and bit PCR95 in PCR9. SI2 CS PCR95 Pin function 0 0 -- 1 0 -- 1 1 --
P95 input pin P95 output pin SI2 input pin CS output pin
Note: * Before entering power-down mode, if this pin is set to SI2 input pin by bit SI2 in PMR2, it should be kept from floating by external connection or should be set to general I/O use by clearing bit SI2 to 0 prior to state transition.
Rev. 3.00, 12/94, page 145 of 334
Table 7-30 Port 9 Pin Functions (cont)
Pin P94/SCK2 Selection Method and Pin Function Functions are switched as follows by means of bit SCK2* in PMR2, bits PS1, PS0* in serial control register 2 (SCR2), and bit PCR94 in PCR9. SCK2 PS1, 0 PCR94 Pin function 0 0 -- 1 Not 11 -- 1 11 --
P94 input pin P94 output pin SCK2 output pin SCK2 input pin
Note: * Before entering power-down mode, if this pin is set to SCK2 input pin by bit SCK2 in PMR2 and bits PS1-PS0 in SCR2, it should be kept from floating by external connection, or else should be set to some other use by changing bits SCK2 and bits PS1, PS0 prior to state transition. On setting bits PS1, PS0 in SCR2, see 11.2.3, Serial Control Register 2 (SCR2). P93/SO1* Functions are switched as follows by means of bit SO1 in PMR2 and bit PCR93 in PCR9. SO1 PCR93 Pin function 0 0 1 1 -- SO1 output pin
P93 input pin P93 output pin
Note: * PMOS on/off can be controlled for the P93/SO1 pin by means of the SO1PMOS bit in PMR3. For details see 10.2.6, Port Mode Register 3 (PMR3). P92/SI1 Functions are switched as follows by means of bit SI1* in PMR2 and bit PCR92 in PCR9. SI1 PCR92 Pin function 0 0 1 1 -- SI1 input pin
P92 input pin P92 output pin
Note: * Before entering power-down mode, if this pin is set to SI1 input pin by bit SI1 in PMR2, it should be kept from floating by external connection or should be set to general I/O use by clearing bit SI1 to 0 prior to state transition.
Rev. 3.00, 12/94, page 146 of 334
Table 7-30 Port 9 Pin Functions (cont)
Pin P91/SCK1 Selection Method and Pin Function Functions are switched as follows by means of bit SCK1 in PMR2,* bits SMR3-SMR0 in serial mode register 1 (SMR1), and bit PCR91 in PCR9. SCK1 SMR13 to 0 PCR91 Pin function 0 0 -- 1 Not 1111 -- 1 1111 --
P91 input pin P91 output pin SCK1 output pin SCK1 input pin
Note: * Before entering power-down mode, if this pin is set to SCK1 input pin by bit SCK1 in PMR2 and bits SMR13 to SMR10 in SMR1, it should be kept from floating by external connection, or else should be set to some other use by changing bits SCK1 bit and bits SMR13 to SMR10 prior to state transition. On setting bits SMR13 to SMR10 in SMR1, see 10.2.1, Serial Mode Register 1 (SMR1). P90/PWM Functions are switched as follows by means of bit PWM in PMR2 and bit PCR90 in PCR9. PWM PCR90 Pin function 0 0 1 1 -- PWM output pin
P90 input pin P90 output pin
7.10.4 Pin States Table 7-31 shows the port 9 pin states in each operating mode. Table 7-31 Port 9 Pin States
Pins P97/UD, P96/SO2, P95/SI2/CS, P94/SCK2, P93/SO1, P92/SI1, P91/SCK1, P90/PWM Reset Sleep Standby High impedance Watch High impedance Subactive High impedance Active Normal operation
High Contents impedance or retained pulled up
Rev. 3.00, 12/94, page 147 of 334
7.11 Port A
7.11.1 Overview Port A is a 2-bit standard I/O. Figure 7-12 shows the pin configuration.
Port A
PA 1 (I/O) PA 0 (I/O)
Figure 7-12 Port A Pin Configuration 7.11.2 Register Configuration and Description Table 7-32 shows the port A register configuration. Table 7-32 Port A Registers
Name Port control register A Port data register A Abbrev. PCRA PDRA R/W W R/W Initial Value H'FC H'FC Address H'FFEA H'FFDA
1.
Bit
Port control register A (PCRA)
7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 PCRA 1 0 W 0 PCRA 0 0 W
Initial value Read/Write
PCRA is an 8-bit register for controlling whether each of port A pins PA1 and PA0 functions as an input or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes it an input pin. Bits 7-2 are reserved; they are always read as 1, and cannot be modified. PCRA is a write-only register. All bits are read as 1. Upon reset, PCRA is initialized to H'FC.
Rev. 3.00, 12/94, page 148 of 334
2.
Bit
Port data register A (PDRA)
7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 PDRA 1 0 R/W 0 PDRA 0 0 R/W
Initial value Read/Write
PDRA is an 8-bit register for storing the data of port A pins PA1 and PA0. When port A is read while PCRA is set to 1, the PDRA values will be read directly, without any influence of the pin states. When port A is read while PCRA is cleared to 0, the pin states will be read. Bits 7-2 are reserved; they always read as 1, and cannot be modified. Upon reset, PDRA is initialized to H'FC. 7.11.3 Pin Functions Table 7-33 shows the port A pin functions. Table 7-33 Port A Pin Functions
Pin PA1, PA0 Selection Method and Pin Function Functions are switched as follows by means of the bits in PCRA. PCRAn Pin function 0 PAn input pin 1 PAn output pin (n = 1, 0)
7.11.4 Pin States Table 7-34 shows the port A pin states in each operating mode. Table 7-34 Port A Pin States
Pins PA1, PA0 Reset High impedance or pulled up Sleep Contents retained Standby High impedance Watch High impedance Subactive High impedance Active Normal operation
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Section 8 Timers
8.1 Overview
The H8/3724 and H8/3754 Series provides on chip two prescalers (Prescaler S and Prescaler W) with different input clocks, and five timers (Timers A through E). Prescaler S is a 13-bit counter using the system clock ( = fOSC/2) as its input clock. Its output is divided among timers A to C and timer E, for which it is used as operating clock. Prescaler W is a 5-bit counter running on the subclock (SUB = fX/8). Its divided output is used for time-base operation by timer A. Table 8-1 outlines the functions of timers A through E. Table 8-1 Timer A-E Functions
Name Functions Operating Clock (internal) Event Input Pin Waveform Output Pin -- -- Remarks -- --
Timer A * 8-bit interval timer * Time base for clock
8 to 8192 -- (choice of 8 sources) SUB/32 (choice of 4 overflow periods) P10/IRQ0 /8 to /8192 (choice of 7 sources)
Timer B * 8-bit reload timer * Interval operation possible * Event counting use Timer C * 8-bit reload timer * Interval operation possible * Event counting use * Choice of count-up or count-down Timer D * 8-bit event counter Timer E * 8-bit reload timer * Interval operation possible
--
--
P11/IRQ1 /8 to /8192 (choice of 7 sources)
--
Count-up/ count-down can be controlled by software or hardware.
--
P16/EVENT -- P15/IRQ5/ TMOE
-- Can output square wave with 50% duty factor
-- /8 to /8192 (choice of 8 sources)
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8.1.1 Prescaler Operation 1. Prescaler S (PSS) Prescaler S is a 13-bit counter using the system clock ( = fOSC/2) as its input clock. It counts up once per period. At system reset, prescaler S is initialized to H'0000. Upon return to active mode the count-up begins. In standby mode, watch mode, and subactive mode, the system clock () pulse generator stops, so prescaler S also stops functioning. In such cases its value is reset to H'0000. The CPU cannot read or write prescaler S data. The output from prescaler S is shared by timers A-C and E as well as serial communication interfaces 1 and 2. The divider ratio can be set separately for each on-chip peripheral function. 2. Prescaler W (PSW) Prescaler W is a 5-bit counter using the subclock (SUB = fX/8) as its input clock. At system reset, prescaler W is initialized to H'00. Upon return to active mode the count-up begins. Even in standby mode, watch mode, or subactive mode, prescaler W continues functioning so long as clock signals are supplied to pins X1 and X2. Prescaler W can be reset by setting 1's in bits TMA3 and TMA2 of timer mode register A (TMA). Output from prescaler W can used as the operating clock for timer A, in which case timer A functions as a time base. Figure 8-1 shows the clock signals supplied by prescalers S and W to peripheral modules.
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/2 to /8192 OSC1 OSC2 System f OSC clock pulse generator Divider 1/2 Prescaler S Timers A to C and E; serial communication interface 1 and 2
SUB /32 X1 X2 Subclock pulse generator fX Divider 1/8 SUB Prescaler W Timer A
System clock selection (LSON bit in system control register 1)
CPU, ROM, RAM, registers, flags, I/O
Figure 8-1 Clock Supply
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8.2 Timer A
8.2.1 Overview Timer A is an 8-bit interval timer. It can be connected to a 32.768 kHz crystal oscillator for use as a clock time base. 1. Features The main features of timer A are given below. * Runs on any of eight different internal clock sources (/8192, /4096, /2048, /512, /256, /128, /32, /8). When timer A is used as a time base, a choice of four overflow periods (2 s, 1 s, 0.5 s, 125 ms) is possible (using a 32.768 kHz crystal oscillator). An interrupt request is raised when the counter overflows.
*
* 2.
Block diagram Figure 8-2 shows a block diagram of timer A.
SUB SUB/32 TCA
/128
/8192, /4096, /2048 /512, /256, /128, /32, /8 Prescaler S (PSS)
/256
/16
/64
Interval timer overflow
IRRTA
Note: * Can be selected only when the input clock to TCA is the output from prescaler W ( SUB/32). Notation: TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag (interrupt request register 2)
Figure 8-2 Block Diagram
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Internal data bus
32 kHz crystal oscillator
1/8
Prescaler W (PSW)
TMA
3.
Register configuration Table 8-2 shows the register configuration of timer A.
Table 8-2 Timer A Registers
Name Timer mode register A Timer counter A Abbrev. TMA TCA R/W R/W R Initial Value H'F0 H'00 Address H'FFC0 H'FFC1
8.2.2 Register Descriptions 1.
Bit Initial value Read/Write
Timer mode register A (TMA)
7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 TMA3 0 R/W 2 TMA2 0 R/W 1 TMA1 0 R/W 0 TMA0 0 R/W
TMA is an 8-bit read/write register for selecting the prescaler and input clock. Upon reset, TMA is initialized to H'F0. Bits 7 to 4: Reserved bits Bits 7 to 4 are reserved; they are always read as 1, and cannot be modified. Bit 3: Prescaler select (TMA3) Bit 3 selects either prescaler S or prescaler W as the clock input source for timer A.
Bit 3 TMA3 0 1 Description Prescaler S (PSS) used as clock input source for timer A. Prescaler W (PSW) used as clock input source for timer A. (initial value)
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Bits 2 to 0: Clock select (TMA2 to TMA0) Bits 2 to 0 select the clock input to TCA. The selection is made as follows based on the combination of these and bit TMA3.
Bit 3 TMA3 Bit 2 TMA2 Bit 1 TMA1 Bit 0 TMA0 Description Prescaler divider rate (interval timer) or overflow period (time base) 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 Note: = fOSC/2 0 1 PSS, /8192 (initial value) PSS, /4096 PSS, /2048 PSS, /512 PSS, /256 PSS, /128 PSS, /32 PSS, 8 PSW, 2 s PSW, 1 s PSW, 0.5 s PSW, 125 ms PSW and TCA are reset Time-base mode Operation mode Interval timer mode
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2.
Bit
Timer counter A (TCA)
7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 2 TCA2 0 R 1 TCA1 0 R 0 TCA0 0 R
Initial value Read/Write
TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA). TCA values can be read by the CPU at any time. TCA is cleared by setting bits TMA3 and TMA2 of TMA to 1. When TCA overflows, the IRRTA bit in interrupt request register 2 (IRR2) is set to 1. Upon reset, TCA is initialized to H'00. 8.2.3 Timer Operation Timer A is an 8-bit timer which can be used either as an interval timer or, if a 32.768 kHz crystal oscillator is connected, as a clock time base. 1. Operation as interval timer When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, timer counter A (TCA)TCA is reset to H'00 and bit TMA3 is cleared to 0, so count-up resumes immediately after reset, without stopping operation as an interval counter. The clock signal on which timer A runs is set by bits TMA2 to 0 in TMA; any of eight internal clock signals output by prescaler S can be selected. After the count value in TCA reaches H'FF, the next clock signal input causes timer A to overflow, setting bit IRRTA to 1 in interrupt request register 2 (IRR2). If bit IENTA = 1 in interrupt enable register 2 (IENR2), an interrupt is requested of the CPU.* At overflow, the TCA count value goes back to H'00, and count-up begins anew. In other words, in this mode timer A functions as an interval timer that generates an overflow output at regular intervals of 256 input clock pulses. Note: * For details on interrupts, see 3.2.2, Interrupts.
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2.
Operation as clock time base
When bit TMA3 in TMA is set to 1, timer A functions as a time base for a time clock. The overflow period of timer A is set by bits TMA1 and 0 in TMA. A choice of four periods is available, based on the clock signals output by prescaler W. 3. Count initialization
When bits 3 and 2 of TMA are both set to 1, PSW and TCA are initialized (i.e., cleared to 0 and stopped). From this initialized state, if 1, 0 are written to bits 3 and 2, respectively, Timer A begins counting from 0 in time base mode. From the initialized state, if 0, 1 or 0, 0 is written to TMA bits 3 and 2, timer A begins counting from 0 in interval timer mode. However, since prescaler S (PSS) has not been initialized, the time period between writing to bits 3 and 2 and the first count of timer operation will vary.
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8.3 Timer B
8.3.1 Overview Timer B is an 8-bit up-counter, which counts up each time a clock pulse is input. This timer has two operation modes, interval and auto reload. 1. Features The main features of timer B are given below. * Runs on any of seven internal clock sources (/8192, /2048, /512, /256, /128, /32, /8) or an external clock (can be used to count external events). An interrupt request is raised when the counter overflows.
* 2.
Block diagram Figure 8-3 shows a block diagram of timer B.
TMB Internal data bus IRRTB
Prescaler S (13 bits)
TCB
IRQ 0
TLB
Notation: TMB: Timer mode register B TCB: Timer counter B TLB: Timer load register B IRRTB: Timer B overflow interrupt request flag (interrupt request register 2)
Figure 8-3 Block Diagram
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3.
Pin configuration Table 8-3 shows the timer B pin configuration.
Table 8-3 Pin Configuration
Name Event input pin Abbrev. P10/IRQ0 I/O Input Function Timer B event input
4.
Register configuration Table 8-4 shows the register configuration of timer B.
Table 8-4 Timer B Registers
Name Timer mode register B Timer counter B Timer load register B Abbrev. TMB TCB TLB R/W R/W R W Initial Value H'78 H'00 H'00 Address H'FFC2 H'FFC3 H'FFC3
8.3.2 Register Descriptions 1.
Bit Initial value Read/Write
Timer mode register B (TMB)
7 TMB7 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 TMB2 0 R/W 1 TMB1 0 R/W 0 TMB0 0 R/W
TMB is an 8-bit read/write register for selecting the auto-reload function and input clock. Upon reset, TMB is initialized to H'78. Bit 7: Auto-reload function select (TMB7) Bit 7 selects whether timer B is used as a internal timer or auto-reload timer.
Bit 7 TMB7 0 1 Description Interval timer function selected. Auto-reload function selected. (initial value)
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Bits 6 to 3: Reserved bits Bits 6 to 3 are reserved; they always read as 1, and cannot be modified. Bits 2 to 0: Clock select (TMB2 to TMB0) Bits 2 to 0 select the clock input to TCB. External clock counting can be triggered by either the rising or falling edge of clock input.
Bit 2 TMB2 0 0 0 0 1 1 1 1 Bit 1 TMB1 0 0 1 1 0 0 1 1 Bit 0 TMB0 0 1 0 1 0 1 0 1 Description Internal clock: count using /8192. Internal clock: count using /2048. Internal clock: count using /512. Internal clock: count using /256. Internal clock: count using /128. Internal clock: count using /32. Internal clock: count using /8. External clock (P10/IRQ0): count from rising or falling edge.* (initial value)
Note: * External clock edge selection is made by setting bit IEG0 in the IRQ edge select register (IEGR). For details see 3.2.3 2, IRQ edge select register (IEGR).
2.
Bit
Timer counter B (TCB)
7 TCB7 0 R 6 TCB6 0 R 5 TCB5 0 R 4 TCB4 0 R 3 TCB3 0 R 2 TCB2 0 R 1 TCB1 0 R 0 TCB0 0 R
Initial value Read/Write
TCB is an 8-bit read-only up-counter, which is incremented by internal or external clock input. The clock source for input to this counter is selected by bits TMB2 to TMB0 in timer mode register B (TMB). TCB values can be read by the CPU at any time. When TCB overflows from H'FF to H'00 or to the value set in TLB, the IRRTB bit in interrupt request register 2 (IRR2) is set to 1. TCB is allocated to the same address as timer load register B (TLB). Upon reset, TCB is initialized to H'00.
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3.
Bit
Timer load register B (TLB)
7 TLB7 0 W 6 TLB6 0 W 5 TLB5 0 W 4 TLB4 0 W 3 TLB3 0 W 2 TLB2 0 W 1 TLB1 0 W 0 TLB0 0 W
Initial value Read/Write
TLB is an 8-bit write-only register for setting the reload value of timer counter B (TCB). When a reload value is set in TLB, at the same time this value is loaded to timer counter B (TCB) as well, and TCB starts counting up from that value. When TCB overflows during operation in auto-reload mode, the TLB value is loaded in TCB. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks. The same address is allocated to TLB as to TCB. Upon reset, TLB is initialized to H'00. 8.3.3 Timer Operation Timer B is an 8-bit multifunction timer. It can be used as an interval or auto-reload timer, or, depending on the input pin combination, as an event counter. 1. Timer B operation modes Timer B is an 8-bit up-counter which is incremented each time a clock pulse is input. The two operation modes, interval and auto-reload, are explained below. * Operation as interval timer When bit TMB7 in timer mode register B (TMB) is cleared to 0, timer B functions as an 8-bit interval timer. Upon reset, timer counter B (TCB) is reset to H'00 and bit TMB7 is cleared to 0, so count-up resumes immediately after reset, without stopping operation as an interval counter. The clock signal on which timer B runs is set by bits TMB2 to TMB0 in TMB; any of seven internal clock signals output by prescaler S can be selected, or an external clock input at pin P10/IRQ0. After the count value in TCB reaches H'FF, the next clock signal input causes timer B to overflow, setting bit IRRTB to 1 in interrupt request register 2 (IRR2). If bit IENTB = 1 in interrupt enable register 2 (IENR2), an interrupt is requested of the CPU.* At overflow, the TCB count value goes back to H'00, and count-up begins anew.
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When timer B is functioning as an interval timer (bit TMB7 = 0) and a value is set in timer load register B (TLB), this value is loaded at the same time in TCB. Note: * For details on interrupts, see 3.2.2, Interrupts. * Operation as auto-reload timer Setting bit TMB7 in TMB to 1 causes timer B to function as an 8-bit auto-reload timer. When a reload value is set in TLB, that value is loaded at the same time to TCB, becoming the value from which TCB starts its count. After the count value in TCB reaches H'FF, the next clock signal input causes timer B to overflow. The TLB value is then loaded to TCB, and the count continues from that value. This means that overflow periods can be set within a range from 1 to 256 input clocks, depending on the TLB value. The explanation of operation clock sources and interrupts in auto-reload mode is the same as for interval mode. In auto-reload mode (bit TMB7 = 1), resetting the TLB value also initializes TCB. 2. Operation on external clock Timer B can operate on an external clock input at pin P10/IRQ0. External clock operation is selected by setting bits TMB2-0 in timer mode register B to all 1's (111). The TCB count is triggered by either the rising or falling edge of input at pin P10/IRQ0. When timer B is used to count external event input, bit IRQC0 in port mode register 1 (PMR1) should be set to 1, and bit IEN0 in interrupt enable register 1 (IENR1) should be cleared to 0 to disable interrupt requests at IRQ0.
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8.4 Timer C
8.4.1 Overview Timer C is an 8-bit up/down counter that counts up or down for every input clock pulse. This timer has two operation modes, interval and auto reload. 1. Features The main features of timer C are given below. * Runs on any of seven internal clock sources (/8192, /2048, /512, /256, /128, /32, /8) or an external clock (can be used to count external events). An interrupt request is raised when the counter overflows. Can be switched between up- and down-counting by software or hardware control.
* * 2.
Block diagram Figure 8-4 shows a block diagram of timer C.
Prescaler S
TMC Internal data bus IRRTC
UD TCC IRQ 1
TLC Notation: TMC: Timer mode register C TCC: Timer counter C TLC: Timer load register C IRRTC: Timer C overflow interrupt request flag (interrupt request register 2)
Figure 8-4 Block Diagram
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3.
Pin configuration Table 8-5 shows the timer C pin configuration.
Table 8-5 Pin Configuration
Name Event input pin Up-/down-count selection pin Abbrev. P11/IRQ1 P97/UD I/O Input Input Function Timer C event input Timer C up/down control
4.
Register configuration Table 8-6 shows the register configuration of timer C.
Table 8-6 Timer C Registers
Name Timer mode register C Timer counter C Timer load register C Abbrev. TMC TCC TLC R/W R/W R W Initial Value H'18 H'00 H'00 Address H'FFC4 H'FFC5 H'FFC5
8.4.2 Register Descriptions 1.
Bit Initial value Read/Write
Timer mode register C (TMC)
7 TMC7 0 R/W 6 TMC6 0 R/W 5 TMC5 0 R/W 4 -- 1 -- 3 -- 1 -- 2 TMC2 0 R/W 1 TMC1 0 R/W 0 TMC0 0 R/W
TMC is an 8-bit read/write register for auto-reload function selection, counter up/down control, and input clock selection. Upon reset, TMC is initialized to H'18.
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Bit 7: Auto-reload function select (TMC7) Bit 7 selects whether timer C is used as an interval timer or auto-reload timer.
Bit 7 TMC7 0 1 Description Interval timer function selected. Auto-reload function selected. (initial value)
Bit 6: Counter up/down control 1 (TMC6) This bit selects whether up/down control of timer counter C (TCC) is by hardware control using pin P97/UD, or by software control using bit TMC5. Bit 5: Counter up/down control 2 (TMC5) This bit selects whether TCC is used for counting up or down. Its setting is valid when bit TMC6 = 0. Bits TMC6 and TMC5 are set as follows.
Bit 6 TMC6 0 0 1 Bit 5 TMC5 0 1 * Description TCC is used as an up-counter. TCC is used as a down-counter. TCC up/down control is by input at pin P97/UD. TCC is a down-counter if UD pin input is high level, and an up-counter if UD input is low level. (initial value)
Note: * Don't care.
Bits 4 and 3: Reserved bits Bits 4 and 3 are reserved; they are always read as 1, and cannot be modified. Bits 2 to 0: Clock select (TMC2 to TMC0)
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Bits 2 to 0 select the clock input to TCC. External clock counting can be triggered by either the rising or falling edge of clock input.
Bit 2 TMC2 0 0 0 0 1 1 1 1 Bit 1 TMC1 0 0 1 1 0 0 1 1 Bit 0 TMC0 0 1 0 1 0 1 0 1 Description Internal clock: count using /8192. Internal clock: count using /2048. Internal clock: count using /512. Internal clock: count using /256. Internal clock: count using /128. Internal clock: count using /32. Internal clock: count using /8. External clock (P11/IRQ1): count from rising or falling edge.* (initial value)
Note: * External clock edge selection is made by setting bit IEG1 in the IRQ edge select register (IEGR). For details see 3.2.3 2, IRQ edge select register (IEGR).
2.
Bit
Timer counter C (TCC)
7 TCC7 0 R 6 TCC6 0 R 5 TCC5 0 R 4 TCC4 0 R 3 TCC3 0 R 2 TCC2 0 R 1 TCC1 0 R 0 TCC0 0 R
Initial value Read/Write
TCC is an 8-bit read-only up-/down-counter, which is incremented or decremented by internal or external clock input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode register C (TMC). TCC values can be read by the CPU at any time. When TCC overflows (from H'FF to H'00 or to the value set in TLC) or underflows (from H'00 to H'FF or to the value set in TLC), the IRRTC bit in interrupt request register 2 (IRR2) is set to 1. TCC is allocated to the same address as timer load register C (TLC). Upon reset, TCC is initialized to H'00.
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3.
Bit
Timer load register C (TLC)
7 TLC7 0 W 6 TLC6 0 W 5 TLC5 0 W 4 TLC4 0 W 3 TLC3 0 W 2 TLC2 0 W 1 TLC1 0 W 0 TLC0 0 W
Initial value Read/Write
TLC is an 8-bit write-only register for setting the reload value of TCC. When a reload value is set in TLC, at the same time this value is loaded to timer counter C (TCC) as well, and TCC starts counting up or down from that value. When TCC overflows or underflows during operation in auto-reload mode, the TLC value is loaded in TCC. Accordingly, overflow and underflow periods can be set within the range of 1 to 256 input clocks. The same address is allocated to TLC as to TCC. Upon reset, TLC is initialized to H'00. 8.4.3 Timer Operation Timer C is an 8-bit multifunction timer. It can be used as an interval or auto-reload timer, or, depending on the input pin combination, as an event counter. 1. Timer C operation modes Timer C is an 8-bit up-/down-counter which is incremented or decremented each time a clock pulse is input. The two operation modes, interval and auto-reload, are explained below. * Operation as interval timer When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit interval timer. Upon reset, timer counter C (TCC) is initialized to H'00 and TMC to H'18, so count-up resumes immediately after reset, without stopping operation as an interval counter. The clock signal on which timer C runs is set by bits TMC2 to TMC0 in TMC; any of seven internal clock signals output by prescaler S can be selected, or an external clock input at pin P11/IRQ1. Either software or hardware control can be used to determine whether TCC counts up or down, depending on the setting of bit TMC6 in TMC. When software control is selected, the up/down setting is made in bit TMC5. Hardware control is by pin P97/UD.
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After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to overflow (underflow), setting bit IRRTC to 1 in interrupt request register 2 (IRR2). If bit IENTC = 1 in interrupt enable register 2 (IENR2), an interrupt is requested of the CPU.* At overflow (underflow), the TCC count value goes back to H'00 (H'FF), and count-up or count-down begins anew. When timer C is functioning as an interval timer (bit TMC7 = 0) and a value is set in timer load register C (TLC), this value is loaded at the same time in TCC. Note: * For details on interrupts, see 3.2.2, Interrupts. * Operation as auto-reload timer Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a reload value is set in TLC, that value is loaded at the same time to TCC, becoming the value from which TCC starts its count. After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to overflow (underflow). The TLC value is then loaded to TCC, and the count continues from that value. This means that overflow (underflow) periods can be set within a range from 1 to 256 input clocks, depending on the TLC value. The explanation of operation clock sources, up/down control, and interrupts in auto-reload mode is the same as for interval mode. In auto-reload mode (bit TMC7 = 1), resetting the TLC value also initializes TCC. 2. Operation on external clock Timer C can operate on an external clock input at pin P11/IRQ1. External clock operation is selected by setting bits TMC2 to TMC0 in timer mode register C to all 1's (111). The TCC count is triggered by either the rising or falling edge of input at pin P11/IRQ1. When timer C is used to count external event input, bit IRQC1 in port mode register 1 (PMR1) should be set to 1, and bit IEN1 in interrupt enable register 1 (IENR1) should be cleared to 0 to disable interrupt requests at IRQ1. 3. TCC up/down control by hardware TCC up/down control for timer C can be by input at pin P97/UD. When bit TMC6 in TMC is set to 1, a high-level input at the UD pin selects a down-counter, while a low-level input changes it to an up-counter.
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When using input at pin UD for this control, set the UP/DOWN bit in port mode register 2 (PMR2) to 1.
8.5 Timer D
8.5.1 Overview Timer D is an 8-bit event counter, which is incremented each time an external event is input. Counting of external events can be triggered by the rising or falling edge of that input. 1. Features The main features of timer D are given below. * * 2. Choice of rising or falling edge for external event counting. An interrupt request is raised when the counter overflows. Block diagram Figure 8-5 shows a block diagram of timer D
TMD Internal data bus
EVENT
TCD
Notation: TMD: Timer mode register D IRRTD TCD: Timer counter D IRRTD: Timer D overflow interrupt request flag (interrupt request register 2)
Figure 8-5 Block Diagram
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3.
Pin configuration Table 8-7 shows the timer D pin configuration.
Table 8-7 Pin Configuration
Name Event input pin Abbrev. P16/EVENT I/O Input Function Timer D event input
4.
Register configuration Table 8-8 shows the register configuration of timer D.
Table 8-8 Timer D Registers
Name Timer mode register D Timer counter D Abbrev. TMD TCD R/W R/W* R Initial Value H'7E H'00 Address H'FFC6 H'FFC7
Note: * Writing to bit 7 of TMD is possible only when writing 1 to clear the counter.
8.5.2 Register Descriptions 1.
Bit Initial value Read/Write
Timer mode register D (TMD)
7 CLR 0 W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 EDG 0 R/W
TMD is an 8-bit read/write register for clearing timer counter D (TCD), and for selecting whether input at the external event pin is sensed at the rising or falling edge. Bit 7: Counter clear (CLR) Bit 7 initializes TCD to H'00.
Bit 7 CLR 0 1 Description After 1 is written to this bit to initialize TCD, it is cleared to 0 by hardware. Initializes TCD to H'00. (initial value)
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Bits 6 to 1: Reserved bits Bits 6 to 1 are reserved; they always read as 1, and cannot be modified. Bit 0: Edge select (EDG) Bit 0 selects the rising or falling edge of input at external event pin P16/EVENT.
Bit 0 EDG 0 1 Description TCD count-up starts at falling edge of input at pin P16/EVENT. TCD count-up starts at rising edge of input at pin P16/EVENT. (initial value)
2.
Bit
Timer counter D (TCD)
7 TCD7 0 R 6 TCD6 0 R 5 TCD5 0 R 4 TCD4 0 R 3 TCD3 0 R 2 TCD2 0 R 1 TCD1 0 R 0 TCD0 0 R
Initial value Read/Write
TCD is an 8-bit read-only up-counter, which is incremented by external clock input at pin P16/EVENT. The rising or falling edge of clock input is selected by the EDG bit in timer mode register D (TMD). TCD values can be read by the CPU at any time. When TCD overflows from H'FF to H'00, the IRRTD bit in interrupt request register 2 (IRR2) is set to 1. Upon reset, TCD is initialized to H'00.
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8.5.3 Timer Operation 1. Operation on external clock Timer D operates on external clock input at pin P16/EVENT, used as an event input pin. The rising or falling edge of this input is selected by the EDG bit in timer mode register D (TMD). After the count value in TCD reaches H'FF, the next clock signal input causes timer D to overflow, setting bit IRRTD in interrupt request register 2 (IRR2) to 1 . If bit IENTD = 1 in interrupt enable register 2 (IENR2), an interrupt is requested of the CPU.* At overflow, the TCD count value goes back to H'00, and count-up begins anew. TCD can be cleared by setting 1 in the CLR bit of TMD. When external event input is used, the EVENT bit in port mode register 1 (PMR1) should be set to 1. Note: * For details on interrupts, see 3.2.2, Interrupts.
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8.6 Timer E
8.6.1 Overview Timer E is an 8-bit up-counter, which counts up each time a clock pulse is input. This timer has two operation modes, interval and auto reload. In addition, it can output a square wave with a 50% duty factor, using overflow signals or prescaler S signals. 1. Features The main features of timer E are given below. * Runs on any of eight internal clock sources (/8192, /4096, /2048, /512, /256, /128, /32, /8). An interrupt request is raised when the counter overflows. Prescaler signals can be divided to produce a fixed-frequency output with a 50% duty factor. When = 4 MHz, output is 1.95 kHz or 3.9 kHz. When = 2 MHz, output is 0.98 kHz or 1.95 kHz. * Using overflow signals, it can produce square wave output of any frequency with a 50% duty factor.
* *
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2.
Block diagram Figure 8-6 shows a block diagram of timer E.
TME TLE Internal data bus IRRTE Latched to TMOE output
Prescaler S
TCE
Notation: TME: Timer mode register E TCE: Timer counter E TLE: Timer load register E IRRTE: Timer E overflow interrupt request flag (interrupt request register 2)
Figure 8-6 Block Diagram 3. Pin configuration Table 8-9 shows the timer E pin configuration. Table 8-9 Pin Configuration
Name Timer E waveform output pin Abbrev. P15/IRQ5/TMOE I/O Output Function Timer E output
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4.
Register configuration Table 8-10 shows the register configuration of timer E.
Table 8-10 Timer E Registers
Name Timer mode register E Timer counter E Timer load register E Port mode register 4 Abbrev. TME TCE TLE PMR4 R/W R/W R W R/W Initial Value H'78 H'00 H'00 H'0F Address H'FFC8 H'FFC9 H'FFC9 H'FFEE
8.6.2 Register Descriptions 1.
Bit Initial value Read/Write
Timer mode register E (TME)
7 TME7 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 TME2 0 R/W 1 TME1 0 R/W 0 TME0 0 R/W
TME is an 8-bit read/write register for selecting the auto-reload function and input clock. Upon reset, TME is initialized to H'78. Bit 7: Auto-reload function select (TME7) Bit 7 selects whether timer E is used as an interval timer or auto-reload timer.
Bit 7 TME7 0 1 Description Interval timer function selected. Auto-reload function selected. (initial value)
Bits 6 to 3: Reserved bits Bits 6 to 3 are reserved; they always read as 1, and cannot be modified.
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Bits 2 to 0: Clock select (TME2 to TME0) Bits 2 to 0 select the clock input to TCE.
Bit 2 TME2 0 0 0 0 1 1 1 1 Bit 1 TME1 0 0 1 1 0 0 1 1 Bit 0 TME0 0 1 0 1 0 1 0 1 Description Internal clock: count using /8192. Internal clock: count using /4096. Internal clock: count using /2048. Internal clock: count using /512. Internal clock: count using /256. Internal clock: count using /128. Internal clock: count using /32. Internal clock: count using /8. (initial value)
2.
Bit
Timer counter B (TCE)
7 TCE7 0 R 6 TCE6 0 R 5 TCE5 0 R 4 TCE4 0 R 3 TCE3 0 R 2 TCE2 0 R 1 TCE1 0 R 0 TCE0 0 R
Initial value Read/Write
TCE is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TME2 to TME0 in timer mode register E (TME). TCE values can be read by the CPU at any time. When TCE overflows from H'FF to H'00 or to the value set in TLE, the IRRTE bit in interrupt request register 2 (IRR2) is set to 1. TCE is allocated to the same address as timer load register E (TLE). Upon reset, TCE is initialized to H'00.
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3.
Bit
Timer load register E (TLE)
7 TLE7 0 W 6 TLE6 0 W 5 TLE5 0 W 4 TLE4 0 W 3 TLE3 0 W 2 TLE2 0 W 1 TLE1 0 W 0 TLE0 0 W
Initial value Read/Write
TLE is an 8-bit write-only register for setting the reload value of TCE. When a reload value is set in TLE, at the same time this value is loaded to timer counter E (TCE) as well, and TCE starts counting up from that value. When TCE overflows during operation in auto-reload mode, the TLE value is loaded in TCE. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks. The same address is allocated to TLE as to TCE. Upon reset, TLE is initialized to H'00. 4.
Bit Initial value Read/Write
Port mode register 4 (PMR4)
7 TEO 0 R/W 6 TEO ON 0 R/W 5 FREQ 0 R/W 4 VRFR 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
PMR4 is an 8-bit read/write register, for switching functions of pin P15/IRQ5/TMOE and for controlling waveform output from pin TMOE. Upon reset, PMR4 is initialized to H'0F.
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Bit 7: Timer E output function select (TEO) Bit 6: Timer E output on/off (TEO ON) Bit 5: Fixed frequency select (FREQ) Bit 4: Variable frequency select (VRFR) Functions of pin P15/IRQ5/TMOE are switched as follows, according to the values in bits 7 to 4 of PMR4 and in bit IRQC5 of port mode register 1 (PMR1).
PMR1 Bit 5 IRQC5 0 0 0 0 Bit 7 TEO 0 0 1 1 PMR4 Bit 6 Bit 5 TEO ON FREQ 0 * 0 1 0 * * 0 Bit 4 VRFR 0 * * 0 Pin Function P15 pin P15 pin Description Pin State Standard I/O port (initial value) Standard I/O port
TMOE output pin Low-level output (off) TMOE output pin Fixed-frequency output: (on) (/2048) 1.95 kHz ( = 4 MHz) 0.98 kHz ( = 2 MHz) TMOE output pin Fixed-frequency output: (on) (/1024) 3.9 kHz ( = 4 MHz) 1.95 kHz ( = 2 MHz) TMOE output pin Variable-frequency output: (on) toggled by Timer E overflow IRQ5 input pin External interrupt input
0
1
1
1
0
0 1
1 *
1 *
* *
1 *
Note: * Don't care.
Bits 3 to 0: Reserved bits Bits 3 to 0 are reserved; they always read as 1, and cannot be modified.
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8.6.3 Timer Operation Timer E is an 8-bit up-counter, which counts up each time a clock pulse is input. It functions as an interval or auto-reload timer. It can also output a square wave having a 50% duty factor. Each of these operation modes is explained below. 1. Operation as interval timer When bit TME7 in timer mode register E (TME) is cleared to 0, timer E functions as an 8-bit interval timer. Upon reset, timer counter E (TCE) is reset to H'00 and bit TME7 is cleared to 0, so count-up resumes immediately after reset, without stopping operation as an interval counter. The clock signal on which timer E runs is set by bits TME2 to TME0 in TME; any of eight internal clock signals output by prescaler S can be selected. After the count value in TCE reaches H'FF, the next clock signal input causes timer E to overflow, setting bit IRRTE to 1 in interrupt request register 2 (IRR2). If bit IENTE = 1 in interrupt enable register 2 (IENR2), an interrupt is requested of the CPU.* At overflow, the TCE count value goes back to H'00, and count-up begins anew. When timer E is functioning as an interval timer (bit TME7 = 0) and a value is set in timer load register E (TLE), this value is loaded at the same time in TCE. Note: * For details on interrupts, see 3.2.2, Interrupts. 2. Operation as auto-reload timer Setting bit TME7 in TME to 1 causes timer E to function as an 8-bit auto-reload timer. When a reload value is set in TLE, that value is loaded at the same time to TCE, becoming the value from which TCE starts its count. After the count value in TCE reaches H'FF, the next clock signal input causes timer E to overflow. The TLE value is then loaded to TCE, and the count continues from that value. This means that overflow periods can be set within a range from 1 to 256 input clocks, depending on the TLE value. The explanation of operation clock sources and interrupts in auto-reload mode is the same as for interval mode. In auto-reload mode (bit TME7 = 1), resetting the TLE value also initializes TCE.
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3.
Square wave output A 50% duty square wave can be output at pin P15/IRQ5/TMOE, as set in port mode register 4 (PMR4) and in bit IRQC5 in port mode register 1 (PMR1). When bit VRFR = 0 in PMR4, the square wave has a fixed frequency as designated in the FREQ bit. For details on the frequencies that can be output, see 8.6.2 4, Port mode register 4 (PMR4). When bit VRFR = 1, timer E overflow results in a toggle output alternating between low and high level (see figure 8-7). The overflow period is selected in timer load register E (TLE), with timer E operating in auto-reload mode (bit TME7 = 1). The operating clock can be selected by means of bits TME2 to TME0, resulting in a waveform output of any desired frequency within the range shown in table 8-11.
Timer E value = H'FF
TLE value (auto-reload mode selected)
TMOE output waveform
Timer E interrupt request
Figure 8-7 Square Wave Output Triggered by Timer E Overflow
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Table 8-11 Frequencies of Output Waveforms Triggered by Timer E Overflow
Output Waveform ( = 2 MHz) 1 Count (TLE = H'FF) x 2 Internal Clock /8 (250 kHz) /32 (62.5 kHz) /128 (15.62 kHz) /256 (7.8125 kHz) /512 (3.9062 kHz) /2048 (976.5 Hz) /4096 (488.2 Hz) /8192 (244.1 Hz) Count Time 8 s 32 s 128 s 256 s 512 s 2.048 ms 4.096 ms 8.192 ms Output Frequency 125 kz 31.25 kHz 7.8125 kHz 3.9063 kHz 1.9531 kHz 488.3 Hz 244.1 Hz 122.1 Hz 256 Counts (TLE = H'00) x 2 Count Time 2024 s 8192 s 32.768 ms 65.536 ms 131.072 ms 524.288 ms Output Frequency 488.3 Hz 122.1 Hz 30.5 Hz 15.3 Hz 7.63 Hz 1.91 Hz
1048.576 ms 0.95 Hz 2097.152 ms 0.477 Hz
Output Waveform ( = 4 MHz) 1 Count (TLE = H'FF) x 2 Internal Clock /8 (500 kHz) /32 (125 kHz) /128 (31.25 kHz) /256 (15.625 kHz) /512 (7.8125 kHz) /2048 (1.963 Hz) /4096 (976.52 Hz) /8192 (488.2 Hz) Count Time 4 s 16 s 64 s 128 s 256 s 1.024 ms 2.048 ms 4.096 ms Output Frequency 250 kz 62.5 kHz 15.625 kHz 7.8125 kHz 3.9063 kHz 976.6 Hz 488.3 Hz 244.1 Hz 256 Counts (TLE = H'00) x 2 Count Time 1024 s 4096 s 16.384 ms 32.768 ms 65.536 ms 262.144 ms 524.288 ms Output Frequency 976.6 Hz 244.1 Hz 61.0 Hz 30.5 Hz 15.3 Hz 3.8 Hz 1.91 Hz
1048.576 ms 0.95 Hz
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8.7 Interrupts
Timer A-E interrupts are raised when a timer overflows (underflows). Each timer is assigned its own vector address The priority of interrupts is in the order of timer A (high) to timer E (low). Further details are given in 3.2.2, Interrupts, table 3-2, Interrupt Sources. When an interrupt is raised in timers A-E, the corresponding bit IRRTA-IRRTE in interrupt request register 2 (IRR2) is set to 1. These interrupt flags are not cleared even if the interrupt is accepted. They must be cleared to 0 by software in the interrupt handler routine. Interrupts for each timer may be enabled or disabled independently by means of bits IENTA-IENTE in interrupt enable register 2 (IENR2). For further details see 3.2.3, Interrupt Control Registers.
8.8 Application Notes
Even when the EVENT bit in port mode register 1 (PMR1) is set for use of pin P16/EVENT as P16 pin, it is possible that reading the P16 pin may cause timer D to be incremented. When using timer D, be sure to clear timer counter D (TCD) by means of the CLR bit in timer mode register D (TMD).
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Section 9 14-Bit PWM
9.1 Overview
The H8/3724 and H8/3754 Series LSIs are provided with a 14-bit PWM (pulse width modulator) on chip, which can be used as an digital-to-analog converter by connecting a low pass filter. 9.1.1 Features Features of the 14-bit PWM are as follows. * Choice of two conversion periods A conversion period of 32768/, with a minimum modulation width of 2/ (PWCR0 = 1), or a conversion period of 16384/, with a minimum modulation width of 1/ (PWCR0 = 0), can be chosen. Pulse division method for less ripple
*
9.1.2 Block Diagram Figure 9-1 gives a block diagram of the 14-bit PWM.
PWDRL
PWDRU Internal data bus
/2 /4
PWM waveform generator
P90 /PWM
PMR2 (bit 0) PWCR0 PWCR
Notation: PWDRL: PWM data register L PWDRU: PWM data register U PWCR: PWM control register PMR2: Port mode register 2
Figure 9-1 Block Diagram
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9.1.3 Pin Configuration Table 9-1 shows the output pin assigned to the 14-bit PWM. Table 9-1 Pin Configuration
Name PWM waveform output pin Abbrev. PWM I/O Output Function PWM waveform output
9.1.4 Register Configuration Table 9-2 shows the register configuration of the 14-bit PWM. Table 9-2 Register Configuration
Name PWM control register PWM data register U PWM data register L Abbrev. PWCR PWDRU PWDRL R/W W W W Initial Value H'FE H'C0 H'00 Address H'FFCC H'FFCD H'FFCE
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9.2 Register Descriptions
9.2.1 PWM Control Register (PWCR)
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 PWCR0 0 W
PWCR is an 8-bit write-only register for input clock selection. Upon reset, PWCR is initialized to H'FE. Bits 7 to 1: Reserved bits Bits 7 to 1 are reserved; they always read as 1, and cannot be modified. Bit 0: Clock select (PWCR0) Bit 0 selects the clock supplied to the 14-bit PWM. This bit is for writing only; it always reads as 1.
Bit 0 PWCR0 0 1 Description The input clock is /2 (t = 2/). The conversion period is 16384/, with a minimum modulation width of 1/. (initial value)
The input clock is /4 (t = 4/). The conversion period is 32768/, with a minimum modulation width of 2/.
Notation: t: Period of PWM input clock
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9.2.2 PWM Data Registers U and L (PWDRU, PWDRL)
Bit Initial value Read/Write Bit Initial value Read/Write 7 -- 1 -- 7 0 W 6 -- 1 -- 6 0 W 5 0 W 5 0 W 4 0 W 4 0 W 3 0 W 3 0 W 2 0 W 2 0 W 1 0 W 1 0 W 0 0 W 0 0 W
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
This is a 14-bit write-only register, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL. The contents written to PWDRU and L add up to the high-level width of one PWM wave period. When 14-bit data is written to PWDRU and L, the register contents are latched in the PWM waveform generator, updating the PWM waveform generation data there. The 14-bit data is set as follows. a. b. The lower 8 bit are written to PWDRL. The upper 6 bits are written to PWDRU. Data should always be written in the above sequence, first to PWDRL and then to PWDRU. This is a write-only register, which always reads as 1. Upon reset, PWDRU and L are initialized to H'C000.
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9.3 Operation
When using the 14-bit PWM, set the registers in the following sequence. 1. Set bit PWM in port mode register 2 (PMR2) to 1 so that pin P90/PWM is designated for PWM output. Set bit PWCR0 in PWM control register (PWCR) to select a conversion period of either 32768/ (PWCR0 = 1) or 16384/ (PWCR0 = 0). Set the output waveform data in PWM data register U and L (PWDRU, L). Be sure to write in the correct sequence, from PWDRL to PWDRU. At the same time as data is written to PWDRU, the data in this register will be latched in the PWM waveform generator, updating the PWM waveform generation in synchronization with internal signals. One conversion period consists of 64 pulses, as shown in figure 9-2. The total of high-level pulse widths during this period (TH) corresponds to the data in PWDRU and L. This relation can be represented as follows. TH = (data value in PWDRU and L + 64) x t/2 where t is the PWM input clock period, either 2/ (bit PWCR0 = 0) or 4/ (bit PWCR0 = 1). When the data values in PWDRU, L are between H'3FC0 and H'3FFF, the PWM output will be at high level. When the data value is H'0000, TH = 64 x t/2 = 32 t. Example: In order to obtain a conversion period of 8,192 s, registers are set as follows. When bit PWCR0 = 0, the conversion period is 16384/, so = 2 MHz. In this case tfn = 128 s, with 1/ (resolution) = 0.5 s. When bit PWCR0 = 1, the conversion period is 32768/, so = 4 MHz. In this case tfn = 128 s, with 2/ (resolution) = 0.5 s. Accordingly, a conversion period of 8,192 s is achieved by using a clock frequency () of either 2 MHz or 4 MHz.
2.
3.
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Conversion period t f1 t f2 t f63 t f64
t H1
t H2
t H3
t H63
t H64
TH = t H1 + t H2 + t H3 + . . . + t H64 t f1 = t f2 = t f3 . . . = t f64
Figure 9-2 PWM Output Waveform
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Section 10 SCI1
10.1 Overview
Serial communication interface 1 (SCI1) is for clock-synchronous serial transfer of 8-bit or 16-bit data. 10.1.1 Features The main SCI1 features are as follows. * * Choice of 8-bit or 16-bit data transfer Choice of 8 internal clock sources (/1024, /256, /64, /32, /16, /8, /4, /2) or an external clock Interrupts raised on completion of transfer or when error occurs
*
10.1.2 Block Diagram Figure 10-1 shows a block diagram of SCI1.
SMR1 Prescaler S (13 bits) Octal/Hexadecimal counter 1 (3/4 bits) SPR1 IRRS1
Internal data bus
SO1
SDRL1
SDRU1 SI 1 SCK 1 Notation: SMR1: Serial SPR1: Serial SDRL1: Serial SDRU1: Serial IRRS1: Serial mode register 1 port register 1 data register L1 data register U1 communication interface 1 interrupt request flag (interrupt request register 3)
Figure 10-1 Block Diagram
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10.1.3 Pin Configuration Table 10-1 shows the SCI1 pin configuration. Table 10-1 Pin Configuration
Name SCI1 clock pin SCI1 data input pin SCI1 data output pin Abbrev. SCK1 SI1 SO1 I/O I/O Input Output Function SCI1 clock I/O pin SCI1 received data input pin SCI1 transmit data output pin
10.1.4 Register Configuration Table 10-2 shows the SCI1 register configuration. Table 10-2 SCI1 Registers
Name Serial mode register 1 Serial data register U1 Serial data register L1 Serial port register 1 Port mode register 2 Port mode register 3 Abbrev. SMR1 SDRU1 SDRL1 SPR1 PMR2 PMR3 R/W W R/W R/W R/W R/W R/W Initial Value H'80 Not fixed Not fixed Not fixed H'00 H'97 Address H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFEC H'FFED
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10.2 Register Descriptions
10.2.1 Serial Mode Register 1 (SMR1)
Bit Initial value Read/Write 7 -- 1 -- 6 SMR16 0 W 5 SMR15 0 W 4 SMR14 0 W 3 SMR13 0 W 2 SMR12 0 W 1 SMR11 0 W 0 SMR10 0 W
SMR1 is an 8-bit write-only register, for selecting the operation mode and the prescaler divider ratio. There is also a function for initializing internal states of the serial interface when writing to SMR1. When SMR1 is written to, transfer clock supply to serial data registers U1 and L1 (SDRU1, SDRL1) and to the octal/hexadecimal counter is stopped, and the octal/hexadecimal counter is reset to H'00. Accordingly, writing to the serial mode register while the serial interface is operating will cut off data transmission or receipt, and the serial communication interface 1 interrupt request flag (IRRS1) will be set. Upon reset, SMR1 is initialized to H'80. Bit 7: Reserved bit Bit 7 is reserved; it always reads as 1, and cannot be modified. Bits 6 to 4: Operation mode select (SMR16 to SMR14) Bits 6 to 4 select the SCI1 operation mode.
Bit 6 SMR16 0 Bit 5 SMR15 0 Bit 4 SMR14 0 Description Clock continuous output mode 8-bit transfer mode Clock continuous output mode 16-bit transfer mode (initial value)
SMR15, SMR14 set to value other than 00 1 0 0
SMR15, SMR14 set to value other than 00
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Bits 3 to 0: Clock select (SMR13 to SMR10) Bits 3 to 0 select the clock supplied to SCI1.
Bit 3 Bit 2 Bit 1 SMR13 SMR12 SMR11 0 0 0 Bit 0 Clock SMR10 Pin SCK1 Source 0 SCK1 output Prescaler S 1 0 1 0 1 0 1 0 * * * 0 1 SCK1 output SCK1 output SCK1 output SCK1 output SCK1 output SCK1 output SCK1 output Not used Prescaler S Prescaler S Prescaler S Prescaler S Prescaler S Prescaler S Prescaler S -- Prescaler Divider Ratio /1024 (initial value) /256 /64 /32 /16 /8 /4 /2 -- Transfer Clock Period (s) = 4 MHz = 2 MHz 256 64 16 8 4 2 1 -- -- 512 128 32 16 8 4 2 1 --
1 1 0 1 1 0 * * * 1 1 0 * * * 1 1
SCK1 input
External clock --
--
--
10.2.2 Serial Data Register U1 (SDRU1)
Bit Initial value Read/Write Note: * Not fixed 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 2 * R/W 1 * R/W 0 * R/W
SDRU17 SDRU16 SDRU15 SDRU14 SDRU13 SDRU12 SDRU11 SDRU10
SDRU1 is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit transfer (SDRL1 is used for the lower 8 bits). Data written to SDRU1 is output to SDRL1 starting from the least significant bit (LSB), and in synchronization with the falling edge of the transfer clock. This data is than replaced by LSB-first data input at pin SI1, synchronized with the rising edge of the transfer clock. In this way data is shifted in the direction from most significant bit MSB to LSB. Reading and writing to SDRU1 must be done after data transmission or receipt is complete. If this register is read or written while data transfer is in progress, the data contents cannot be guaranteed. The SDRU1 value upon reset is not fixed.
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10.2.3 Serial Data Register L1 (SDRL1)
Bit Initial value Read/Write Note: * Not fixed 7 6 5 4 3 2 1 0
SDRL17 SDRL16 SDRL15 SDRL14 SDRL13 SDRL12 SDRL11 SDRL10 * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W
SDRL1 is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (SDRU1 is used for the upper 8 bits). In 8-bit transfer, data written to SDRL1 is output to pin SO1 starting from the least significant bit (LSB), and in synchronization with the falling edge of the transfer clock. This data is than replaced by LSB-first data input at pin SI1, synchronized with the rising edge of the transfer clock. In this way data is shifted in the direction from most significant bit MSB to LSB. In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is latched by SDRU1. Reading and writing to SDRL1 must be done after data transmission or receipt is complete. If this register is read or written while data transfer is in progress, the data contents cannot be guaranteed. The SDRL1 value upon reset is not fixed. 10.2.4 Serial Port Register 1 (SPR1)
Bit Initial value Read/Write Note: * Not fixed 7
SO1 LAST BIT
6 -- 1 --
5 -- 1 --
4 -- 1 --
3 -- 1 --
2 -- 1 --
1 -- 1 --
0 -- 1 --
* R/W
SPR1 is an 8-bit read/write register, of which bit 7 connects to the last output stage of SDRL1.
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Bit 7: Extended data bit (SO1 LAST BIT) Bit 7 holds the last bit of transmitted data after transmission ends. Output from pin SO1 can be altered by software by manipulating this bit either before or after transmission. If this bit is written during data transmission, the data contents cannot be guaranteed.
Bit 7 SO1 LAST BIT 0 1 Description Output from pin SO1 is low level. Output from pin SO1 is high level. (initial value)
Bits 6 to 0: Reserved bits Bits 6 to 0 are reserved: they always read as 1, and cannot be modified. 10.2.5 Port Mode Register 2 (PMR2)
Bit Initial value Read/Write 7
UP/ DOWN
6 SO2 0 R/W
5 SI2 0 R/W
4 SCK2 0 R/W
3 SO1 0 R/W
2 SI1 0 R/W
1 SCK1 0 R/W
0 PWM 0 R/W
0 R/W
PMR2 is an 8-bit read/write register, for switching the port 9 pin functions. Bits 3 to 1, in combination with SMR1, set the SCI1 operation mode. Upon reset, PMR2 is initialized to H'00. Bits 3 to 1 are explained here. On bits 7 to 4 and bit 0, see 7.10.2 1, Port Mode Register 2 (PMR2). Bit 3: Pin P93/SO1 function switch (SO1) Bit 3 selects whether pin P93/SO1 functions as P93 I/O pin or as SO1 output pin.
Bit 3 SO1 0 1 Description Pin P93/SO1 functions as P93 I/O pin. Pin P93/SO1 functions as SO1 output pin. Setting bit SCK1 to 1 and clearing bit SI1 to 0 puts SCI1 in transmit mode. (initial value)
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Bit 2: Pin P92/SI1 function switch (SI1) Bit 2 selects whether pin P92/SI1 functions as P92 I/O pin or as SI1 input pin.
Bit 2 SI1 0 1 Description Pin P92/SI1 functions as P92 I/O pin. Pin P92/SI1 functions as SI1 input pin. Setting bit SCK1 to 1 and clearing bit SO1 to 0 puts SCI1 in receive mode. (initial value)
Bit 1: Pin P91/SCK1 function switch (SCK1) Bit 1 selects whether pin P91/SCK1 functions as P91 I/O pin or as SCK1 I/O pin.
Bit 1 SCK1 0 1 Description Pin P91/SCK1 functions as P91 I/O pin. (initial value)
Pin P91/SCK1 functions as SCK1 I/O pin. The direction of clock I/O and the prescaler divider ratio are set in serial mode register 1 (SMR1).
10.2.6 Port Mode Register 3 (PMR3)
Bit Initial value Read/Write 7 -- 1 -- 6
SO2 PMOS
5 CS 0 R/W
4 -- 1 --
3
SO1 PMOS
2 -- 1 --
1 -- 1 --
0 -- 1 --
0 R/W
0 R/W
PMR3 is an 8-bit read/write register, for PMOS on/off switching of the SCI1 and SCI2 data output pins (pins SO1 and SO2), and for controlling SCI2 chip select output (pin SI2/CS). Upon reset, PMR3 is initialized to H'97. Bit 3 is explained here. On bits 6 and 5, see 11.2.5, Port Mode Register 3 (PMR3). Bit 3: Pin SO1 PMOS on/off (SO1PMOS) Bit 3 controls on/off of the pin P93/SO1 PMOS buffer.
Bit 3 S01PMOS 0 1 Description The PMOS buffer of pin P93/SO1 is on, resulting in CMOS output. (initial value)
The PMOS buffer of pin P93/SO1 is off, resulting in NMOS open drain output.
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10.3 Operation
10.3.1 Overview SCI1 sends and receives data in synchronization with a clock pulse. SCI1 operation modes are set by bits 6 to 4 of serial mode register 1 (SMR1) and bits 3 to 1 of port mode register 2 (PMR2) in combination, as shown in table 10-3. Table 10-3 SCI1 Operation Mode Setting
SMR1 SMR16 * * 0 SMR15 * 0 SMR14 * 0 PMR23 0 0 1 0 1 1 SMR15, SMR14 set to value other than 00 1 0 1 Note: * Don't care. PMR2 PMR22 0 0 0 1 1 0 1 1 PMR21 0 1 1 1 1 1 1 1 Operation Mode Serial communication disabled Clock continuous output mode 8-bit send mode 8-bit receive mode 8-bit send/receive mode 16-bit send mode 16-bit receive mode 16-bit send/receive mode
SMR15, SMR14 set to value other than 00
SCI1 consists of SMR1, serial data register U1 (SDRU1), serial data register L1 (SDRL1), serial port register 1 (SPR1), an octal/hexadecimal counter, and a multiplexer. (See figure 10-1.) Pin SCK1 and the transfer clock are controlled by writing data to SMR1. SDRU1 and SDRL1 are used to write data to be sent and to hold received data; these registers can be written to and read by software. Data in these registers is shifted in synchronization with the transfer clock, for input and output at pins SI1 and SO1. SCI1 operation starts with a dummy read of SMR1. The octal/hexadecimal counter is cleared to H'0 by this dummy read, and starts counting anew from the falling edge of the transfer clock (pin SCK1), being incremented by 1 at each transfer clock rising edge. If 8 or 16 transfer clock pulses are input and the counter overflows, or if data send/receive is cut off in progress, the octal/ hexadecimal counter is cleared to H'0. At the same time bit IRRS1 in interrupt request register 3 (IRR3) is set to 1. For more details on interrupts, see 3.2.2, Interrupts.
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10.3.2 Data Transfer Format Figure 10-2 shows the clock-synchronous data transfer format. Data can be sent and received in lengths of 8 bits or 16 bits. Data is sent and received starting from the least significant bit, in LSB-first format. A data segment for transmission is output from the falling edge of the transfer clock pulse until the next falling edge. Receive data is latched from the rising edge of the clock.
SCK 1 LSB SO 1 SI 1 input data latch timing n = 7: 8-bit transfer mode n = 15: 16-bit transfer mode Bit 0 Bit 1 Bit 2 Bit 3 Bit n - 1 MSB Bit n
Figure 10-2 Clock-Synchronous Data Transfer Format 10.3.3 Clock A choice of 8 internal clock sources or an external clock may be used as the transfer clock for serial communication. When an internal clock is used, pin SCK1 is the clock output pin. 10.3.4 Data Transmit/Receive 1. Initializing SCI1 Before data is sent or received, first SCI1 must be initialized by software. This is done by writing the desired transfer conditions in serial mode register 1 (SMR1). 2. Data transmission A send operation takes place as follows. * Bit SO1 in port mode register 2 (PMR2) is set to 1, making pin P93/SO1 the SO1 output pin. Also, bit SCK1 in PMR2 is set to 1, making pin P91/SCK1 the SCK1 I/O pin. If necessary, the SO1PMOS bit in PMR3 is set for NMOS open drain output at pin SO1.
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*
Bit SMR16 in SMR1 is set to 1 or cleared to 0, and bits SMR15-SMR14 are set to a value other than 00, designating 8- or 16-bit transfer mode. The transfer clock is then selected in bits SMR13-SMR10. Writing data to SMR1 initializes the SCI1 internal states. Transfer data is written in serial data register L1 (SDRL1) and serial data register U1 (SDRU1), as follows. 8-bit transfer mode: SDRL1 16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1 A dummy read is made of SMR1. SCI1 starts operating, and data for transmission is output at pin SO1. After data transmission is complete, bit IRRS1 in interrupt request register 3 (IRR3) is set to 1.
*
*
*
If an internal clock source is used, a synchronization clock pulse is output from pin SCK1 at the same time as data is output. After data transmission is complete, the synchronization clock is not output until the next SMR1 dummy read. During this time, pin SO1 continues to output the value of the last bit sent. When an external clock source is used, data is transmitted in synchronization with the clock pulse input at pin SCK1. After data transmission is complete, a send operation is resumed if the synchronization clock continues to be input. Between transmissions, the output value of pin SO1 can be changed by rewriting bit 7 (SO1 LAST BIT) in serial port register 1 (SPR1). Executing an SMR1 dummy read during transmission will result in transmit error, setting bit IRRS1 in IRR3 to 1. 3. Data receipt A receive operation takes place as follows. * Bit SI1 in port mode register 2 (PMR2) is set to 1, making pin P92/SI1 the SI1 input pin. Also, bit SCK1 in PMR2 is set to 1, making pin P91/SCK1 the SCK1 I/O pin. Bit SMR16 in serial mode register 1 (SMR1) is set to 1 or cleared to 0, and bits SMR15- SMR14 are set to a value other than 00, designating 8- or 16-bit transfer mode. The transfer clock is then selected in bits SMR13-SMR10. Writing data to SMR1 initializes the SCI1 internal states. A dummy read is made of SMR1. SCI1 starts operating, and received data is input at pin SI1.
*
*
Rev. 3.00, 12/94, page 200 of 334
* *
After data receipt is complete, bit IRRS1 in interrupt request register 3 (IRR3) is set to 1. Received data is read in SDRL1 and SDRU1, as follows. 8-bit transfer mode: SDRL1 16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1
If an internal clock source is used, a dummy read of SMR1 immediately starts a data receive operation. The synchronization clock is output from pin SCK1. When an external clock source is used, after the dummy read of SMR1, data is received in synchronization with the clock pulse input at pin SCK1. After data receipt is complete, a receive operation is resumed if the synchronization clock continues to be input. Executing an SMR1 dummy read during receipt will result in data receive error, setting bit IRRS1 in IRR3 to 1. 4. Simultaneous data transmission/receipt A simultaneous send/receive operation takes place as follows. * Bits SO1, SI1, and SCK1 in PMR2 are all set to 1, designating SO1 output pin, SI1 pin, and SCK1 pin. If necessary, the SO1PMOS bit in PMR3 is set for NMOS open drain output at pin SO1. Bit SMR16 in SMR1 is set to 1 or cleared to 0, and bits SMR15-SMR14 are set to a value other than 00, designating 8- or 16-bit transfer mode. The transfer clock is then selected in bits SMR13-SMR10. Writing data to SMR1 initializes the SCI1 internal states. Transfer data is written in SDRL1 and SDRU1, as follows. 8-bit transfer mode: SDRL1 16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1 A dummy read is made of SMR1. SCI1 starts operating, data for transmission is output at pin SO1, and received data is input at pin SI1. After data transmission and receipt is complete, bit IRRS1 in IRR3 is set to 1. Received data is read from SDRL1 and SDRU1. 8-bit transfer mode: SDRL1 16-bit transfer mode: Upper byte in SDRU1, lower byte in SDRL1
*
*
*
* *
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In simultaneous data transmission/receipt, the send operation and receive operation described in 10.2.4 2 and 10.2.4 3 above take place at the same time. See those sections for further details. During a send/receive operation, a dummy read to SMR1 will result in transmit/receive error, setting bit IRRS1 in IRR3 to 1. 10.3.5 SCI1 State Transitions There are three internal SCI1 states, as shown in figure 10-3. In serial start pending state, the serial communication interface internal state is initialized. In this state, the serial communication interface does not operate even if a transfer clock signal is input. Executing an SMR1 dummy read in this state changes the state to transfer clock pending state. In transfer clock pending state, when a transfer clock signal is input the octal/hexadecimal counter starts counting up and the serial data register shift begins, thus entering transfer state. If clock continuous output mode has been selected, however, instead of going to transfer state the system will output the clock signal continuously. In transfer state, when 8 or 16 transfer clock cycles are input, or if SMR1 dummy read and SMR1 write are executed, the octal/hexadecimal counter is reset to H'0, and transfer clock pending state is entered. Writing to SMR1 in transfer state will reset the octal/hexadecimal counter to H'0 and change the state to serial start pending state. When the state goes from transfer state to another state, the resetting of the octal/hexadecimal counter to H'0 sets bit IRRS1 in IRR3 to 1. If an internal clock source is selected, a dummy read to SMR1 starts output from the transfer clock, which stops after 8 or 16 clock output cycles. When writing to SMR1 in transfer clock pending state or in transfer state, it is necessary to write to SMR1 again in order to initialize the serial communication interface internal state. After writing to SMR1, the state becomes serial start pending state.
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Serial start (SMR1 dummy read) pending state octal counter = 000 or hexadecimal counter = 0000 transfer clock disabled.
SMR1 write
SMR1 dummy read (serial start)
8 or 16 transfer clock cycles (internal clock) (IRRS1 1)
SMR1 write (IRRS1 1)
Transfer clock pending state octal counter = 000 or hexadecimal counter = 0000
Transfer clock
Transfer state octal counter = 000 or / hexadecimal counter =0000 /
SMR1 dummy read (serial start) (IRRS1 1) 8 or 16 transfer clock cycles (external clock)
Figure 10-3 SCI1 State Transitions 10.3.6 Transfer Clock Error Detection In transfer state, if an extraneous pulse is superimposed on the proper transfer clock signal due to external noise or the like, SCI1 may function incorrectly. Transfer clock error can be detected by means of a procedure like that shown in figure 10-4. In transfer clock pending state, if more than the normal 8 or 16 transfer clock cycles are mistakenly input, the SCI1 state will change from transfer state to transfer clock pending state and then back to transfer state. After bit IRRS1 in interrupt request register 3 (IRR3) is cleared to 0, writing a value in serial mode register 1 (SMR1) changes the state to serial start pending, and bit IRRS1 is again set to 1.
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Transfer complete (IRRS1 1) Interrupt disabled IRRS1 0
SMR1 write Yes Transfer clock error processing
IRRS1 = 1? No Normal completion
Figure 10-4 Typical Procedure for Transfer Clock Error Detection 10.3.7 Interrupts SCI1 interrupts are raised for transfer complete and for transmit/receive error. These interrupts are assigned a common vector address. When SCI1 transfer is complete, or when transmit/receive error occurs before transfer is complete, bit IRRS1 in interrupt request register 3 (IRR3) is set to 1. SCI1 interrupt requests can be enabled or disabled in bit IENS1 of interrupt enable register 3 (IENR3). For further details, see 3.2.2, Interrupts.
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Section 11 SCI2
11.1 Overview
Serial communication interface 2 (SCI2) has a 32-byte data buffer, for clock-synchronous serial transfer of up to 32 bytes of data in one operation. 11.1.1 Features The main SCI2 features are as follows. * * * Automatic transfer of up to 32 bytes of data Operates on internal clock sources (/8, /4, /2) or an external clock Interrupts raised on completion of transfer or when error occurs
11.1.2 Block Diagram Figure 11-1 shows a block diagram of SCI2.
Prescaler S (13 bits)
Shift clock generator circuit
SCK 2
Bit counter
SCR2
STAR
Address decoder and R/W controller
Byte counter
Comparator circuit
IRRS2
Data buffer (32 bytes)
EDAR
Shift register
SO 2 SI2 /CS
Internal data bus Notation: STAR: Start address register EDAR: End address register IRRS2: Serial communication interface 2 interrupt request flag (interrupt request register 3)
Figure 11-1 Block Diagram
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11.1.3 Pin Configuration Table 11-1 shows the SCI2 pin configuration. Table 11-1 Pin Configuration
Name SCI2 clock pin SCI2 data input pin SCI2 data output pin SCI2 chip select output pin Abbrev. SCK2 SI2 SO2 CS I/O I/O Input Output Output Function SCI2 clock I/O pin SCI2 received data input pin SCI2 transmit data output pin SCI2 chip select output pin
Note: Function switching of pins P94/SCK2, P95/SI2/CS, and P96/SO2 is done in port mode register 2 (PMR2) and port mode register 3 (PMR3). On PMR2, see 7.10.2 1, Port mode register 2 (PMR2).
11.1.4 Register Configuration Table 11-2 shows the SCI2 register configuration. Table 11-2 SCI2 Registers
Name 32-byte data buffer Start address register End address register Serial control register 2 Status register Port mode register 2 Port mode register 3 Abbrev. -- STAR EDAR SCR2 STSR PMR2 PMR3 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Not fixed H'E0 H'E0 H'E0 H'E0/H'E8 H'00 H'97 Address H'FF80 to H'FF9F H'FFA0 H'FFA1 H'FFA2 H'FFA3 H'FFEC H'FFED
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11.2 Register Descriptions
11.2.1 Start Address Register (STAR)
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 STA4 0 R/W 3 STA3 0 R/W 2 STA2 0 R/W 1 STA1 0 R/W 0 STA0 0 R/W
STAR is an 8-bit read/write register, for designating the transfer start address in the memory space from H'FF80 to H'FF9F allocated to the 32-byte data buffer. The 32 bytes from H'00 to H'1F designated by the lower 5 bits of STAR (bits STA4 to STA0) correspond to address space H'FF80 to H'FF9F. Data is sent or received continuously using the area defined in STAR and in the end address register (EDAR). Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Upon reset, STAR is initialized to H'E0. 11.2.2 End Address Register (EDAR)
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 EDA4 0 R/W 3 EDA3 0 R/W 2 EDA2 0 R/W 1 EDA1 0 R/W 0 EDA0 0 R/W
EDAR is an 8-bit read/write register, for designating the transfer end address in the memory space from H'FF80 to H'FF9F allocated to the 32-byte data buffer. The 32 bytes from H'00 to H'1F designated by the lower 5 bits of EDAR (bits EDA4 to EDA0) correspond to address space H'FF80 to H'FF9F. Data is sent or received continuously using the area defined in STAR and EDAR. When the same value is designated in both STAR and EDAR, only that one byte of data is transferred. Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Upon reset, EDAR is initialized to H'E0.
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11.2.3 Serial Control Register 2 (SCR2)
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 I/O 0 R/W 3 GAP2 0 R/W 2 GAP1 0 R/W 1 PS1 0 R/W 0 PS0 0 R/W
SCR2 is an 8-bit read/write register, for selecting SCI2 transmit or receive, for gap insertion during continuous transfer, and for transfer clock selection. Upon reset, SCR2 is initialized to H'E0. Bits 7 to 5: Reserved bits Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Bit 4: Transmit/receive select (I/O) Bit 4 selects SCI2 transmit or receive mode.
Bit 4 I/O 0 1 Description SCI2 is in receive mode. SCI2 is in transmit mode. (initial value)
Bits 3 and 2: Gap insertion (GAP2 to GAP1) Bits 3 and 2 designate the length of transfer clock high-level intervals between data divisions, in data continuous transmit/receive operation. These settings are valid when an internal clock source is selected as the transfer clock (PS1 and 0 11). Data divisions may be placed every 8 bits or 16 bits; this is selected in bit GIT in the status register (STSR).
Bit 3 GAP2 0 0 1 1 Bit 2 GAP1 0 1 0 1 Description Transfer clock keeps the same duty factor even at data divisions. (initial value)
Transfer clock extends high level by one clock cycle at data divisions. Transfer clock extends high level by two clock cycles at data divisions. Transfer clock extends high level by eight clock cycles at data divisions.
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Bits 1 and 0: Transfer clock select (PS1 to PS0) Bits 1 and 0 select one of three internal clock sources or external clock.
Bit 1 Bit 2 PS1 PS0 Pin SCK2 0 0 1 1 0 1 0 1 SCK2 output SCK2 output SCK2 output SCK2 input Prescaler Divider Ratio /4 /8 -- Transfer Clock Period = 4 MHz = 2 MHz = 1 MHz 1 s 2 s 4 s -- 2 s 4 s 8 s -- 1 s 2 s --
Clock Source Prescaler S Prescaler S Prescaler S External clock
/2 (initial value) *
Note: * Can be set, but operation is not guaranteed.
11.2.4 Status Register (STSR)
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4
SO2 LAST BIT
3 OVR
*1
2 WT 0 R/W*2
1 GIT 0 R/W
0 STF 0 R/W
0 R/W
R/W*2
Notes: 1. Not fixed 2. Cleared to 0 by write operation to STSR.
STSR is an 8-bit register indicating the SCI2 operation state, error status, etc. Writing to this register during data transmission may cause misoperation. Upon reset, STSR is initialized to H'E0 or H'E8. Bits 7 to 5: Reserved bits Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. Bit 4: Extended data bit (SO2 LAST BIT) Bit 4 holds the last bit of transmitted data after transmission ends. Output from pin SO2 can be altered by software by manipulating this bit either before or after transmission. Writing this bit during data transmission may cause misoperation.
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Bit 4 SO2 LAST BIT 0 1
Description Output from pin SO2 is low level. Output from pin SO2 is high level. (initial value)
Bit 3: Overrun flag (OVR) If the data transferred is longer than the set buffer size, or if an extraneous pulse signal is imposed on the correct transfer clock due to external noise or the like, SCI2 goes to overrun state and bit 3 is set to 1.
Bit 3 OVR 0 1 Description [Clear conditions] When STSR is written to. [Set conditions] When overrun occurs during a transfer operation. (initial value)
Bit 2: Waiting flag (WT) When a read or write instruction to the 32-byte buffer is executed during data transfer, the instruction is ignored, and bit 2 is set to 1 along with bit IRRS2 in interrupt request register 3 (IRR3).
Bit 2 WT 0 1 Description [Clear conditions] When STSR is written to. (initial value)
[Set conditions] When a read/write to the 32-byte buffer occurs during a transfer operation.
Bit 1: Gap interval flag (GIT) Bit 1 designates whether the extension to the transfer clock high-level intervals, as designated in bits GAP2 and GAP1 in serial control register 2 (SCR2), occurs at 8-bit or 16-bit data divisions. This setting is valid only for internal clock operation.
Bit 1 GIT 0 1 Description The GAP2 and GAP1 setting is valid for 16-bit divisions. The GAP2 and GAP1 setting is valid for 8-bit divisions. (initial value)
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Bit 0: Start/busy flag (STF) Setting bit 0 to 1 starts an SCI2 transfer operation. This bit stays at 1 during transfer, and is cleared to 0 after transfer is complete. It can thus be used as a busy flag as well. Clearing this bit to 0 during transfer aborts the transfer, initializing SCI2. The contents of the 32-byte data buffer and of other registers besides STSR are unchanged when this happens.
Bit 0 STF 0 Explanation [Read access] Indicates that transfer operation has stopped. [Write access] Stops transfer. 1 [Read access] Indicates transfer in progress. [Write access] Starts transfer. (initial value)
11.2.5 Port Mode Register 3 (PMR3)
Bit Initial value Read/Write 7 -- 1 -- 6
SO2 PMOS
5 CS 0 R/W
4 -- 1 --
3
SO1 PMOS
2 -- 1 --
1 -- 1 --
0 -- 1 --
0 R/W
0 R/W
PMR3 is an 8-bit read/write register, for controlling PMOS on/off of SCI1 and SCI2 output pins (pin P93/SO1 and pin P96/SO2), and for controlling SCI2 chip select output (pin SI2/CS). Upon reset, PMR3 is initialized to H'97. On bit 3, see 10.2.6, Port Mode Register 3 (PMR3). Bit 7: Reserved bit Bit 7 is reserved; it is always reads as 1, and cannot be modified.
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Bit 6: Pin SO2 PMOS on/off (SO2PMOS) Bit 6 controls PMOS on/off for pin P96/SO2.
Bit 6 SO2PMOS 0 1 Description The PMOS buffer of pin P96/SO2 is on, resulting in CMOS output. (initial value)
The PMOS buffer of pin P96/SO2 is off, resulting in NMOS open drain output.
Bit 5: Chip select output select (CS) Bit 5 sets pin P95/SI2/CS to CS output pin. It is set in combination with bit SI2 in port mode register 2 (PMR2). The CS output pin function is valid only in transmit mode.
PMR2 Bit 5 SI2 0 PMR3 Bit 5 CS 0 1 1 0 1 Description Pin P95/SI2/CS functions as P95 I/O pin. Pin P95/SI2/CS functions as P95 I/O pin. Pin P95/SI2/CS functions as SI2 input pin. Pin P95/SI2/CS functions as CS output pin. (initial value)
Bits 4 and 2 to 0: Reserved bits These bits are reserved; they are always read as 1, and cannot be modified.
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11.3 Operation
11.3.1 Overview SCI2 has a 32-byte data buffer, making possible continuous transfer of up to 32 bytes of data with one operation. SCI2 sends and receives data in synchronization with a clock pulse. Selection of transmit or receive mode and of the transfer clock is made in serial control register 2 (SCR2). The start address register (STAR) and end address register (EDAR) designate the area within the 32-byte data buffer for holding transfer data. The address space from H'FF80 to H'FF9F is allocated to this data buffer. The start and end positions of the transfer data area are indicated in the lower 5 bits of STAR and EDAR. After parameters have been set in port mode register 2 (PMR2), port mode register 3 (PMR3), SCR2, STAR, and EDAR, then when the STF bit of the status register (STSR) is set to 1, SCI2 begins a transfer operation. STF keeps a value of 1 during transfer, and is cleared to 0 when transfer is complete. The STF bit can thus be used as a busy flag. Clearing the STF bit to 0 during transfer stops the transfer operation and initializes SCI2. The contents of the data buffer and of other registers are unchanged in this case. During transfer, the CPU cannot read or write the data buffer. If a write instruction is issued it is ignored; it has the same effect as a NOP instruction except that it adds to the number of states. A read access during transfer yields H'FF. When transfer is complete, or if a data buffer read or write occurs during transfer, bit IRRS2 in interrupt request register 3 (IRR3) is set to 1. In case of overrun error or a data buffer read or write during transfer, bits OVR and WT of STSR are each set to 1. Note: If the start address is set to a value higher than the end address, the result is as shown in figure 11-2. After data is transferred to H'FF9F it starts back at H'FF80 and continues to the end address.
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H'FF80 End
H'00 End address
Start
Start address
H'FF9F
H'1F
Figure 11-2 Operation When Start Address Exceeds End Address 11.3.2 Clock A choice of three internal clock sources or an external clock may be used as the transfer clock. When an internal clock is selected, pin SCK2 becomes the clock output pin. 11.3.3 Data Transfer Format Figure 11-3 shows the SCI2 data transfer format. Data is sent and received starting from the least significant bit, in LSB-first format. A data segment for transmission is output from the falling edge of the transfer clock pulse until the next falling edge. Receive data is latched from the rising edge of the clock. When SCI2 operates on an internal clock and is in transmit mode, a gap may be inserted at data divisions (every 8 bits or 16 bits). During this gap, the transfer clock stays at high level for the designated number of clock cycles (see figures 11-4 through 11-6). The CS output remains at low level during the gap. Gap insertion and the length of the gap are designated in bits GAP2 and GAP 1 in serial control register 2 (SCR2). Bit GIT in the status register (STSR) is used to designate whether gaps occur at 8-bit or 16-bit intervals.
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CS
SCK2
SO2
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Held
Don't care
Figure 11-3 Clock-Synchronous Data Transfer Format
Does not go to low level SCK 2 output Bit 14 (Bit 6) Bit 15 (Bit 7)* Bit 16 (Bit 8) Bit 17 (Bit 9)
SO2 SI 2 input data latch timing
Note: * When bit GIT = 1, a gap is inserted at 8-bit intervals.
Figure 11-4 Gap Insertion for 1 Clock Cycle (bits GAP2-GAP1 = 01)
Does not go to low level SCK 2 output Bit 14 (Bit 6) Bit 15 (Bit 7)* Bit 16 (Bit 8)
SO2 SI 2 input data latch timing
Note: * When bit GIT = 1, a gap is inserted at 8-bit intervals.
Figure 11-5 Gap Insertion for 2 Clock Cycles (bits GAP2-GAP1 = 10)
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Transfer clock x 8 SCK 2 output Bit 14 (Bit 6) Bit 15 (Bit 7)* Bit 16 (Bit 8)
SO2 SI 2 input data latch timing
Note: * When bit GIT = 1, a gap is inserted at 8-bit intervals.
Figure 11-6 Gap Insertion for 8 Clock Cycles (bits GAP2-GAP1 = 11) 11.3.4 Data Transmit/Receive 1. SCI2 initialization Serial communication on SCI2 first of all requires that SCI2 be initialized by software. This involves clearing bit STF in the status register (STSR) to 0, then selecting pin functions and transfer mode in port mode register 2 (PMR2), port mode register 3 (PMR3), start address register (STAR), end address register (EDAR), and serial control register 2 (SCR2). 2. Data transmission A send operation takes place as follows. * Bit SO2 in port mode register 2 (PMR2) is set to 1, making pin P96/SO2 the SO2 output pin. If necessary, the SO2PMOS bit and CS bit in PMR3 are set for NMOS open drain output at pin SO2 and for chip select output at pin P95/SI2/CS. Data for transmission is written to the 32-byte data buffer (H'FF80 to H'FF9F). The transfer start address is set in the lower 5 bits of STAR. The transfer end address is set in the lower 5 bits of EDAR. In SCR2, transmit mode (bit I/O = 1), the transfer clock, and gap insertion (internal clock operation only) are set. Data intervals for gap insertion are set in bit GIT of STRS, then bit STF is set to 1. Setting bit STF starts the transmit operation.
* * * *
*
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*
After data transmission is complete, bit IRRS2 in interrupt request register 3 (IRR3) is set to 1, and bit STF in STSR is cleared to 0.
If an internal clock source is used, a synchronization clock pulse is output from pin SCK2 at the same time as data is output. After data transmission is complete, the synchronization clock is not output until bit STF is again set. During this time, pin SO2 continues to output the value of the last bit of the data sent immediately preceding. When an external clock source is used, data is transmitted in synchronization with the clock pulse input at pin SCK2. After data transmission is complete, no send operation takes place even if the synchronization clock continues to be input; and pin SO2 continues to output the value of the last bit of the data sent immediately preceding. Between transmissions, the output value of pin SO2 can be changed by rewriting bit SO2 LAST BIT in STSR. Executing a read or write of the data buffer during transmission will cause bit IRRS2 in IRR3 to be set to 1. Bit WT in STSR will likewise be set to 1. 3. Data receipt A receive operation takes place as follows. * * Bit SI2 in port mode register 2 (PMR2) is set to 1, making pin P95/SI1/CS the SI2 input pin. An area for holding received data is allocated in the 32-byte data buffer by indicating the start address in the lower 5 bits of the start address register (STAR). The transfer end address is set in the lower 5 bits of the end address register (EDAR). In serial control register 2 (SCR2), receive mode (bit I/O = 0) and the transfer clock are designated. Bit STF of the status register (STSR) is set to 1, starting the receive operation. After data receipt is complete, bit IRRS2 in interrupt request register 3 (IRR3) is set to 1, and bit STF is cleared to 0. Received data is read from the data buffer.
* *
* *
*
If an internal clock source is used, setting bit STF to 1 in STSR immediately starts a data receive operation. The synchronization clock is output from pin SCK2.
Rev. 3.00, 12/94, page 217 of 334
When an external clock source is used, after bit STF is set, data is received in synchronization with the clock pulse input at pin SCK2. After data receipt is complete, no receive operation takes place until bit STF is again set, even if the synchronization clock continues to be input. Executing a read or write of the data buffer during data receipt will cause bit IRRS2 in IRR3 to be set to 1. Bits WT and OVR in STSR will be set to 1 in this case or if an overrun error occurs. When SCI2 operates on an internal clock and is in transmit mode, a gap may be inserted at data divisions (every 8 bits or 16 bits). During this gap, the transfer clock stays at high level for the designated number of clock cycles (see figures 11-4 through 11-6). Gap insertion and the length of the gap are designated in bits GAP2 and GAP 1 of SCR2. Bit GIT of STSR is used to designate whether gaps occur at 8-bit or 16-bit intervals.
11.4 Interrupts
SCI2 interrupts are raised for transfer completion when the data buffer is read or written during transfer. These interrupts are assigned a common vector address. When the above conditions occur in SCI2, bit IRRS2 in interrupt request register 3 (IRR3) is set to 1. SCI2 interrupt requests can be enabled or disabled in bit IENS2 of interrupt enable register 3 (IENR3). For further details, see 3.2.2, Interrupts. When overrun error occurs, or when a read or write of the data buffer is attempted during transfer, the OVR and WT bits in the status register (STSR) are set to 1. These bits can be used to determine the cause of error.
11.5 Application Notes
1. Do not write to any register during transfer (while bit STF of STSR is set to 1), since this can cause misoperation. During data receipt, bit SI2 in port mode register 2 (PMR2) should be set to 1 and bit CS in port mode register 3 (PMR3) should be cleared to 0. If bit CS = 1 while bit SI2 = 1, selecting the CS pin function, a receive operation may result in received data error. When an external clock is selected as the transfer clock in the transmit mode, the transfer clock input timing must not exceed the rated transfer hold time.
2.
3.
Rev. 3.00, 12/94, page 218 of 334
Section 12 VFD Controller/Driver
12.1 Overview
The H8/3724 and H8/3754 Series LSIs are equipped with an on-chip vacuum tube fluorescent display (VFD) controller/driver and high-voltage, high-current pins, for direct VFD driving. 12.1.1 Features The VFD controller/driver has the following main features. * Maximum of 28 segment pins and 16 digit pins (20 segment pins, eight digit pins, and eight switched segment/digit pins). Brightness can be adjusted in 8 steps (dimmer function). Display places can be changed automatically. Digit pins and segment pins can be switched to use as general-purpose high-voltage pins. Key scan interval on/off function Interrupt raised when key scan interval starts
* * * * *
12.1.2 Block Diagram Figure 12-1 shows a block diagram of the VFD controller/driver.
Internal data bus
VFDR
DBR
VFSR
IRRKS
Display timing generator circuit
VFD display RAM
Digit pins
Segment pins
Notation: VFDR: VFD digit control register DBR: Digit beginning register VFSR: VFD segment control register IRRKS: Key scan interrupt request flag (bit 6 of interrupt request register 3)
Figure 12-1 Block Diagram
Rev. 3.00, 12/94, page 219 of 334
12.1.3 Pin Configuration Table 12-1 shows the VFD controller/driver pin configuration. Table 12-1 Pin Configuration
Name Digit/segment pins Abbrev. FD0/FS7 to FD7/FS0 I/O Output Function Digit or segment pins for vacuum fluorescent tube (function selected in DBR for each bit) Digit pins for vacuum fluorescent tube Segment pins for vacuum fluorescent tube
Digit pins Segment pins
FD8 to FD15 FS8 to FS27
Output Output
12.1.4 Register Configuration Table 12-2 shows the VFD controller/driver register configuration. Table 12-2 Register Configuration
Name VFD display RAM VFD segment control register VFD digit control register Digit beginning register Abbrev. -- VFSR VFDR DBR R/W R/W R/W R/W R/W Initial Value Not fixed H'20 H'00 H'20 Address H'FEC0 to H'FEFF H'FFB9 H'FFBA H'FFBB
Rev. 3.00, 12/94, page 220 of 334
12.2 Register Descriptions
12.2.1 VFD Digit Control Register (VFDR)
Bit Initial value Read/Write 7 FLMO 0 R/W 6 DM2 0 R/W 5 DM1 0 R/W 4 DM0 0 R/W 3 DR3 0 R/W 2 DR2 0 R/W 1 DR1 0 R/W 0 DR0 0 R/W
VFDR is an 8-bit read/write register for control of digit output. Upon reset, VFDR is initialized to H'00. Bit 7: VFD mode bit (FLMO) Bit 7 designates the time per digit/key scan (Tdigit) and the dimmer resolution (Tdimmer).
Bit 7 FLMO 0 1 Digit/Key Scan Time (Tdigit) Period 1536/ (initial value) 768/ = 4 MHz 384 s 192 s = 2 MHz 768 s 384 s Dimmer Resolution (Tdimmer) Period 96/ (initial value) 48/ = 4 MHz 24 s 12 s = 2 MHz 48 s 24 s
The frame period (Tframe) is calculated using the equation below. Tframe = Tdigit x (D + K) D: Number of digit pins used K: 1 if key scan is used; 0 if not used
Rev. 3.00, 12/94, page 221 of 334
Bits 6 to 4: Digit waveform select (DM2 to DM0) Bits 6 to 4 select the digit waveform.
Bit 6 DM2 0 Bit 5 DM1 0 Bit 4 DM0 0 1 1 0 1 1 0 0 1 1 0 1
*1
Digit Signal Waveform (initial value)
Tdigit*2 Tdimmer*2
*1
Notes: 1. Segment signal change timing 2. On Tdimmer and Tdigit, see under FLMO bit.
Rev. 3.00, 12/94, page 222 of 334
Bits 3 to 0: Digit pin select (DR3 to DR0) Bits 3 to 0, in combination with bits 3 to 0 of the digit beginning register (DBR), designate the digit pins used.
Bit 3 DR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 DR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 DR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 DR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pins Valid as Digit Pins FD0 to FD15 FD0 to FD14 FD0 to FD13 FD0 to FD12 FD0 to FD11 FD0 to FD10 FD0 to FD9 FD0 to FD8 FD0 to FD7 FD0 to FD6 FD0 to FD5 FD0 to FD4 FD0 to FD3 FD0 to FD2 FD0 to FD1 FD0 (initial value)
Note: On switching between digit and segment use of pins FD0/FS7 to FD7/FS0, which can function as either digit or segment pins, see 12.2.3, Digit Beginning Register (DBR). FDm FDm+1 FDm+2 to FDn-2 FDn-1 FDn Segment data
Figure 12-2 Order of Digit Output
Rev. 3.00, 12/94, page 223 of 334
12.2.2 VFD Segment Control Register (VFSR)
Bit Initial value Read/Write 7 VFLAG 0 R/W 6 KSE 0 R/W 5 -- 1 -- 4 SR4 0 R/W 3 SR3 0 R/W 2 SR2 0 R/W 1 SR1 0 R/W 0 SR0 0 R/W
VFSR is an 8-bit read/write register for control of segment output. Upon reset, VFSR is initialized to H'20. Bit 7: VFD/port switching flag (VFLAG) Bit 7 designates whether pins Pnn/FDnn and Pnn/FSnn are used as VFD pins (FDnn, FSnn) or as general-purpose ports (Pnn).
Bit 7 VFLAG 0 1 Description All of pins Pnn/FDnn and all of pins Pnn/FSnn function as general-purpose ports. (initial value)
Pnn/FDnn and Pnn/FSnn function as VFD pins according to the designations in bits DR3-DR0 in the VFD digit control register (VFDR), bits SR4-SR0 in VFSR, and bits DBR3-DBR0 in the digit beginning register (DBR).
Note: Even when this flag is set to 1, during a key scan interval the segment pins function as general-purpose ports; for this reason, when the flag is read during a key scan interval it is read as 0.
Bit 6: Key scan enable (KSE) Bit 6 selects whether addition of a key scan interval (Tdigit) to the VFD operation frame is allowed or not. The addition of a key scan interval is controlled by the combination of bits DR3 to DR0 in the VFD digit control register (VFDR), bits SR4 to SR0 in VFSR, and bits DBR3 to DBR0 in the digit beginning register (DBR).
Bit 6 KSE 0 1 Description Addition of a key scan interval is not allowed. (initial value)
Addition of a key can interval is allowed. See also under bit 7 (VFLAG) above.
Bit 5: Reserved bit Bit 5 is reserved; it is always read as 1, and cannot be modified.
Rev. 3.00, 12/94, page 224 of 334
Bits 4 to 0: Segment pin select (SR4 to SR0) Bits 4 to 0, in combination with bits 3 to 0 of the digit beginning register (DBR), designate the segment pins used.
Bit4 SR4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 3 SR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 SR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 SR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 SR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pins Valid as Segment Pins FS0 FS0 to FS1 FS0 to FS2 FS0 to FS3 FS0 to FS4 FS0 to FS5 FS0 to FS6 FS0 to FS7 FS0 to FS8 FS0 to FS9 FS0 to FS10 FS0 to FS11 FS0 to FS12 FS0 to FS13 FS0 to FS14 FS0 to FS15 FS0 to FS16 FS0 to FS17 FS0 to FS18 FS0 to FS19 FS0 to FS20 FS0 to FS21 FS0 to FS22 FS0 to FS23 FS0 to FS24 FS0 to FS25 FS0 to FS26 FS0 to FS27
(initial value)
Note: On switching between digit and segment use of pins FD0/FS7 to FD7/FS0, which can function as either digit or segment pins, see 12.2.3, Digit Beginning Register (DBR).
Rev. 3.00, 12/94, page 225 of 334
12.2.3 Digit Beginning Register (DBR)
Bit Initial value Read/Write 7 VFDE 0 R/W 6 DISP 0 R/W 5 -- 1 -- 4 -- 0 R/W 3 DBR3 0 R/W 2 DBR2 0 R/W 1 DBR1 0 R/W 0 DBR0 0 R/W
DBR is an 8-bit read/write register for on/off control of the VFD controller, and for switching functions of pins that can be either digit or segment pins. Bit 7: VFD enable (VFDE) Bit 7 switches the VFD controller on and off.
Bit 7 VFDE 0 1 Description VFD controller is in reset state. VFD controller in running state (initial value)
Note: This flag is set with no relation to whether pins Pnn/FDnn and Pnn/FSnn are used as VFD pins or as general-purpose ports.
Bit 6: Display bit (DISP) Bit 6 switches the display on and off.
Bit 6 DISP 0 1 Description All segment pins (FS) are in non-illuminating state (pull-down state). (initial value) Register and RAM values are unchanged. Digit pins (FD) continue operating. Data for the display RAM is output to segment pins (FS).
Bit 5: Reserved bit Bit 5 is reserved; it is always read as 1, and cannot be modified. Bit 4: Reserved bit Bit 4 is reserved; read and write are possible.
Rev. 3.00, 12/94, page 226 of 334
Bits 3 to 0: Digit/segment pin function switch (DBR3 to DBR0) Bits 3 to 0 designate the first digit pin and the first segment pin of those pins that can function both ways. It is therefore necessary to set bits DR3-DR0 of VFD digit control register (VFDR) and bits SR4-SR0 of VFSR so that the first digit and segment pins are operational. Otherwise these pins will not function.
Bit 3 DBR3 0 0 0 0 0 0 0 0 1 Bit 2 DBR2 0 0 0 0 1 1 1 1 * Bit 1 DBR1 0 0 1 1 0 0 1 1 * Bit 0 DBR0 0 1 0 1 0 1 0 1 * Functions of FD0/FS7 to FD7/FS0 FD0 to FD7 FD1 to FD7, FS7 FD2 to FD7, FS7 to FS6 FD3 to FD7, FS7 to FS5 FD4 to FD7, FS7 to FS4 FD5 to FD7, FS7 to FS3 FD6 to FD7, FS7 to FS2 FD7, FS7 to FS1 FS7 to FS0 (initial value)
Notes: Digit pins (FD) and segment pins (FS) are controlled by both VFDR and VFSR. Note also that during a key scan interval, segment pins (FS) function as general-purpose ports. * Don't care.
Rev. 3.00, 12/94, page 227 of 334
12.3 Operation
12.3.1 Overview The VFD controller/driver may use up to 28 pins as segment pins (FS) and up to 16 pins as digit pins (FD). Of these, 8 pins may be used as either segment or digit pins; their function is switched in the digit beginning register (DBR). The 36 pins assigned to the VFD controller are highvoltage, high-current driver pins, and are capable of direct VFD driving. 12.3.2 Control Part The control part consists of the VFD digit control register (VFDR), VFD segment control register (VFSR), digit beginning register (DBR), display timing generator circuit, and VFD display RAM (see figure 12-1). Display timing is determined by the number of digits used per frame. When the key scan feature is activated, the frame is extended by one digit; during that interval only, segment pins and digit pins may be used as general purpose ports and manipulated by the CPU. Note that digit pins must be in the pull-down state (VFD not illuminated) during the key scan interval. 12.3.3 RAM Bit Correspondence to Digits/Segments Data for VFD display is set in the VFD display RAM at addresses H'FEC0 through H'FEFF. Table 12-3 show the correspondence between digit/segment pins and the VFD display RAM bits.
Rev. 3.00, 12/94, page 228 of 334
Table 12-3 Digit/Segment Pins and VFD Display RAM Bits
Port Seg 8 H'FEC0 H'FEC4 H'FEC8 H'FECC H'FED0 H'FED4 H'FED8 H'FEDC H'FEE0 H'FEE4 H'FEE8 H'FEEC H'FEF1 H'FEF5 H'FEF9 H'FEFD LSB MSB H'FEF0 H'FEF4 H'FEF8 H'FEFC LSB MSB LSB 7 6 5 4 3 2 10 Dig 0 1 2 3 4 5 6 7 8 9 10 11 H'FEED 12 13 14 15 60 61 62 63 64 65 66 67 70 71 72 73 74 75 76 77
Port
37 36 35 34 33 32 31 30 47 46 45 44 43 42 41 40 50 51 52 53 54 55 56 57 60 61 62 63 64 65 66 67
Seg
Dig H'FEC2 H'FEC6 H'FECA H'FECE H'FED2 H'FED6 H'FEDA H'FEDE H'FEE2 H'FEE6 H'FEEA H'FEEE H'FEF2 H'FEF6 H'FEFA H'FEFE LSB MSB H'FEE9 H'FEE5 H'FEE1 H'FEDD H'FED9 H'FED5 H'FED1 H'FECD H'FEC9 H'FEC5 H'FEC1
-- -- -- -- 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
60
0
H'FEC3
61
1
H'FEC7
62
2
H'FECB
63
3
H'FECF
64
4
H'FED3
65
5
H'FED7
66
6
H'FEDB
67
7
H'FEDF
70
8
H'FEE3
71
9
H'FEE7
72
10
H'FEEB
73
11
H'FEEF
74
12
H'FEF3
75
13
H'FEF7
76
14
H'FEFB
77
15
H'FEFF
MSB
Rev. 3.00, 12/94, page 229 of 334
Note: Any RAM area not used for display may be used as general-purpose RAM.
12.3.4 Procedure for Starting Operation The procedure for starting operation of the VFD controller is illustrated here, for a case in which digit pins FD3 to FD15 and segment pins FS5 to FS27 are used. It is assumed here that data has already been written to the VFD display RAM area. * The digit/key scan time and dimmer resolution are set in bit FLMO of the VFD digit control register (VFDR), and the digit waveform is selected in bits DM2-DM0. Bits DR3 to DR0 are set to 0000 making pins FD0 to FD15 operational. The VFLAG bit of VFD segment control register (VFSR) is set to 1, making the selected pins valid as VFD pins. Bit KSE is set for key scan interval on or off. Bits SR4 to SR0 are set to 11011, making pins FS0 to FS27 operational. Bits DBR3-DBR0 in the digit beginning register (DBR) are set to 0011, designating pin FD3 as the first digit pin and pin FS5 as the first segment pin. Bit DISP is set to 1, turning the display on, and bit VFDE is set to 1, starting VFD controller operation.
*
*
12.4 Interrupts
When the key scan interval starts, bit IRRKS in interrupt request register 3 (IRR3) is set to 1. VFD interrupt requests can be enabled or disabled by means of bit IENKS of interrupt enable register 3 (IENR3). For further details, see 3.2.2, Interrupts.
12.5 Occurrence of Flicker when the VFD Register Is Rewritten
The VFD controller/driver is initialized whenever one of its registers (VFDR, VFSR, DBR) is rewritten. If this initialization takes place while the VFD is displaying, the contents displayed just prior to initialization will in some cases remain as an after-image in other digits. (This depends in part on the performance of the fluorescent tubes, but a momentary glow may be visible.) Because of this phenomenon, frequent rewriting of the registers can cause a noticeable after-image that adversely affects the display. This problem can be avoided by employing the following programming sequence when VFD controller/driver registers are rewritten. Sequence 1. 2. 3. 4. Contents DISP = 0 VFLAG = 0 Rewrite register (FLMO, DM0 to DM3, etc.) Wait for at least Tdigit (display time of one digit). (Execute other routines.) If the wait time is too long, the entire display may flicker. Use of the key scan feature allows programming to be done without worrying about wait time. VFLAG = 1 DISP = 1
5. 6.
Rev. 3.00, 12/94, page 230 of 334
Section 13 A/D Converter
13.1 Overview
The H8/3724 and H8/3754 Series LSIs include on chip a resistance-ladder type successiveapproximation A/D converter, which can handle up to eight channels of analog input. 13.1.1 Features The A/D converter has the following main features. * * * * * 8-bit resolution 8 input channels Conversion time: 14.8 s per channel (min, at fosc = 8.38 MHz) Built-in sample-and-hold function Interrupt raised on completion of A/D conversion
Rev. 3.00, 12/94, page 231 of 334
13.1.2 Block Diagram Figure 13-1 shows a block diagram of the A/D converter.
PMR0 (8b) AMR (4b) Port Port Port Port Port Port Port Port + Control logic Control circuitry (successive approximation, interrupt raising, etc.) - R255 R254 R253 R252 R251 Successive approximation changes the reference voltage (VREF) and requests an analog input voltage. RESET LPM (low power mode) ADRR Chopper-type converter Interrupt ADSR Internal data bus MPX
P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7
AVCC
Reference voltage
VREF
R1
AVSS
One of 256 switches is selected by binary search. Each approximation is made eight times, and the ADRR reference voltage is set on the basis of the results. (The eighth value is the same as the analog input voltage.) The internal ladder resistance is 35 k to 40 k typ (reference value). Upon reset and in low-power operation modes (sleep, watch, subactive, or standby modes), the ladder resistance is separated off from AV SS by a switching MOS. The AV CC current at this time is a leakage current Alcc of 1 A or less (reference value). Notation: PMR0: Port mode register 0 AMR: A/D mode register ADSR: A/D start register ADRR: A/D result register IRRAD: A/D conversion complete interrupt request flag (interrupt request register 3) RESET: Signal set to 1 upon reset LPM: Signal set to 1 in low-power operation mode
Figure 13-1 Block Diagram
Rev. 3.00, 12/94, page 232 of 334
13.1.3 Pin Configuration Table 13-1 shows the A/D converter pin configuration. Table 13-1 Pin Configuration
Name Analog power source pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Abbrev. AVCC AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 I/O Input Input Input Input Input Input Input Input Input Input Function Power source and reference voltage of analog part Ground and reference voltage of analog part Analog input channel 0 Analog input channel 1 Analog input channel 2 Analog input channel 3 Analog input channel 4 Analog input channel 5 Analog input channel 6 Analog input channel 7
13.1.4 Register Configuration Table 13-2 shows the A/D converter register configuration. Table 13-2 Register Configuration
Name A/D mode register A/D start register A/D result register Port mode register 0 Abbrev. AMR ADSR ADRR PMR0 R/W R/W R/W R W Initial Value H'78 H'7F Not fixed H'00 Address H'FFBC H'FFBE H'FFBD H'FFEF
Rev. 3.00, 12/94, page 233 of 334
13.2 Register Descriptions
13.2.1 A/D Result Register (ADRR)
Bit Initial value Read/Write Note: * Not fixed 7 ADR7 * R 6 ADR6 * R 5 ADR5 * R 4 ADR4 * R 3 ADR3 * R 2 ADR2 * R 1 ADR1 * R 0 ADR0 * R
The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-todigital conversion. ADRR can be read by the CPU at any time, but the ADRR values during A/D conversion are not fixed. After A/D conversion is complete, the conversion results are sent to ADRR as 8-bit data; this data is held in ADRR until the next conversion operation starts. ADRR is not cleared on reset. 13.2.2 A/D Mode Register (AMR)
Bit Initial value Read/Write 7 AMR7 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 AMR2 0 R/W 1 AMR1 0 R/W 0 AMR0 0 R/W
AMR is an 8-bit read/write register for setting the A/D conversion speed and the analog input pins. Writing to AMR should be done with the A/D start flag (ADSF) cleared to 0 in the A/D start register (ADSR). Upon reset, AMR is initialized to H'78.
Rev. 3.00, 12/94, page 234 of 334
Bit 7: Clock select (AMR7) Bit 7 sets the A/D conversion speed.*1
Bit 7 AMR7 0 1 Conversion Period*2 62/ 31/ = 2 MHz 31 s 15.5 s = 4 MHz 14.8 s --*1 (initial value)
Notes: 1. At a conversion speed of below 14.8 s, operation is not guaranteed. Set bit 7 for a speed of 14.8 s or faster. 2. A/D conversion starts after a value of 1 is written to ADSF. The conversion period starts when the start flag is set and ends when it is reset upon completion of conversion. The actual time during which sample and hold are repeated is called the conversion interval (see figure 13-2).
State EXECUTION MOV B.
WRITE START flag
Conversion interval
Conversion period (31 or 62 states)
Interrupt request flag
IRQ sampling (CPU) Note: IRQ sampling: When conversion is complete, the start flag is reset and the interrupt request flag is set. An interrupt is recognized by the CPU in the last instruction execution state, and the interrupt exception handler is executed after that instruction is completed.
Figure 13-2 Internal Operation of A/D Converter
Rev. 3.00, 12/94, page 235 of 334
Bits 6 to 3: Reserved bits Bits 6 to 3 are reserved; they are always read as 1, and cannot be modified. Bits 2 to 0: Channel select (AMR2 to AMR0) Bits 2 to 0 select the analog input channels. When setting these bits, also set the affected channels in port mode register 0 (PMR0). On channel setting, see 13.2.4, Port Mode Register 0 (PMR0).
Bit 2 AMR2 0 0 0 0 1 1 1 1 Bit 1 AMR1 0 0 1 1 0 0 1 1 Bit 0 AMR0 0 1 0 1 0 1 0 1 Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 (initial value)
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13.2.3 A/D Start Register (ADSR)
Bit Initial value Read/Write 7 ADSF 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
The A/D start register (ADSR) is an 8-bit read/write register for designating the start or stop of A/D conversion. A/D conversion is started by writing 1 to the A/D start flag (ADSF). When conversion is complete, the conversion data is set in the A/D result register (ADRR), and at the same time ADSF is cleared to 0. Bit 7: A/D start flag (ADSF) Bit 7 is for controlling and confirming the start and end of A/D conversion.
Bit 7 ADSF 0 Description [Read access] Indicates that A/D conversion has stopped. [Write access] Stops A/D conversion. 1 [Read access] Indicates A/D conversion in progress. [Write access] Starts A/D conversion. (initial value)
Bits 6 to 0: Reserved bits Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified.
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13.2.4 Port Mode Register 0 (PMR0)
Bit Initial value Read/Write 7 AN7 0 W 6 AN6 0 W 5 AN5 0 W 4 AN4 0 W 3 AN3 0 W 2 AN2 0 W 1 AN1 0 W 0 AN0 0 W
PMR0 is an 8-bit write-only register for designating whether each of the port 0 pins is used as a general-purpose input port or as an analog input channel to the A/D converter. Designation is made separately for each bit of this register. Upon reset, PMR0 is initialized to H'00.
Bit n ANn 0 1 Description Pin P0n/ANn is a general-purpose input port. Pin P0n/ANn is an analog input channel. (n = 0 to 7) (initial value)
13.3 Operation
The A/D converter operates by sequential comparison, and yields its conversion result as 8-bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete. The completion of conversion also sets bit IRRAD in interrupt request register 3 (IRR3) to 1. An A/D conversion complete interrupt is raised if bit IENAD in interrupt enable register 3 (IENR3) is set to 1. If the conversion time or input channels are to be changed in the A/D mode register (AMR) during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation, in order to avoid misoperation.
13.4 Interrupts
When A/D conversion is complete (ADSF: 1 0), bit IRRAD in interrupt request register 3 (IRR3) is set to 1. A/D conversion complete interrupts can be enabled or disabled by means of bit IENAD in interrupt enable register 3 (IENR3). For further details see 3.2.2, Interrupts.
Rev. 3.00, 12/94, page 238 of 334
13.5 Typical Use
A typical example of how the A/D converter can be used is given below, using channel 1 (AN1) as the analog input channel. Figure 13-3 shows the operation timing for this example. 1. Bits AMR2-AMR0 of the A/D mode register (AMR) are set to 001, and bits AN7 to AN0 of port mode register 0 (PMR0) are set to 00000010, making AN1 the analog input channel. A/D interrupts are enabled by setting bit IENAD in interrupt enable register 2 (IENR2) to 1, and A/D conversion is started by setting bit ADSF to 1. When A/D conversion is complete, bit IRRAD in interrupt request register 3 (IRR3) is set to 1, and the A/D conversion results are sent to the A/D result register (ADRR). At the same time ADSF is cleared to 0, and the A/D converter goes to conversion pending state. Bit IENAD = 1, indicating that an A/D conversion complete interrupt has been raised. The A/D interrupt handling routine starts. The A/D conversion results are read and processed. The A/D interrupt handling routine stops processing.
2.
3. 4. 5. 6.
Thereafter, when ADSF is set to 1, A/D conversion starts and steps 2 through 6 take place. Figures 13-4 and 13-5 show flow charts of A/D converter use.
Rev. 3.00, 12/94, page 239 of 334
Interrupt Set* Reset*
Rev. 3.00, 12/94, page 240 of 334
A/D conversion starts Set* Set*
Conversion pending A/D conversion 1
IENAD
ADSF
Channel 1 (AN 1 ) operation states Conversion pending Conversion result read* A/D conversion result 1
A/D conversion 2
Conversion pending Conversion result read * A/D conversion result 2 When the next A/D conversion starts, the previous result is lost.
ADRR
Figure 13-3 Typical A/D Converter Operation Timing
Note: * ( ) indicates instruction execution by software.
START
Set A/D conversion speed and input channels
Disable A/D conversion complete interrupt
Start A/D conversion
Read ADSR
No
Does ADSF = 0? Yes Read ADRR data
Yes
Perform A/D conversion? No END
Figure 13-4 Conceptual Flow Chart of A/D Converter Use (1) (polling by software)
Rev. 3.00, 12/94, page 241 of 334
START
Set A/D converter speed and input channels
Enable A/D conversion complete interrupt
Start A/D conversion
A/D conversion complete interrupt raised? No
Yes
Clear bit IRRAD to 0 in IRR3
Read ADRR data
Yes
Perform A/D conversion? No END
Figure 13-5 Conceptual Flow Chart of A/D Converter Use (2) (interrupts used)
Rev. 3.00, 12/94, page 242 of 334
13.6 Application Notes
1. Data in the A/D result register (ADRR) should be read only when A/D start flag (ADSF) in the A/D start register (ADSR) is cleared to 0. Changing the digital input signal at a nearby pin during an A/D conversion operation may adversely affect conversion accuracy. Pins selected as analog input channels in the A/D mode register (AMR) must also be designated as analog input channels in port mode register 0 (PMR0).
2.
3.
Rev. 3.00, 12/94, page 243 of 334
Rev. 3.00, 12/94, page 244 of 334
Section 14 Electrical Specifications
14.1 Absolute Maximum Ratings
Table 14-1 gives the absolute maximum ratings for the H8/3724 Series. Table 14-1 Absolute Maximum Ratings (provisional values)
Item Supply voltage Programming voltage Analog supply voltage Analog input voltage Pin voltage (standard pins) Pin voltage (high-voltage pins) Operating temperature Storage temperature Symbol VCC VPP AVCC AVIN VT VT Top Tstg Rating -0.3 to +7.0 -0.3 to +14.0 -0.3 to +7.0 -0.3 to AVCC +0.3 -0.3 to VCC +0.3 VCC -45 to VCC +0.3 -20 to +75 -55 to +125 Unit V V V V V V C C Notes 1, 2 1, 2, 3 1, 2 1, 2 1, 2, 4 1, 2, 5 1, 2 1, 2
Notes: 1. Operation in excess of these absolute maximum ratings may result in permanent damage to the LSI. Normally the LSI should be operated within the conditions given under electrical characteristics on the following pages, so as to avoid malfunction and assure maximum reliability. 2. All voltages are based on VSS as a reference voltage. 3. Applies to the ZTATTM version. 4. Applies to standard-voltage pins. 5. Applies to high-voltage pins.
Rev. 3.00, 12/94, page 245 of 334
14.2 HD6473724 and HD6473726 Electrical Characteristics
14.2.1 HD6473724 and HD6473726 DC Characteristics Table 14-2 gives the allowable current values of the HD6473724 and HD6473726, and table 14-3 gives the electrical characteristics. Table 14-2 Allowable Current Sink Values Conditions: VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C
Item Allowable input current (into LSI) Allowable output current (from LSI) Allowable output current (from LSI) Total allowable input current (into LSI) Total allowable output current (from LSI) Symbol IO -IO -IO IO -IO Rating 2 2 20 50 150 Unit mA mA mA mA mA Notes 1, 2 2, 3 3, 4 5 6
Notes: 1. Allowable input current means the maximum current that can flow from each I/O pin to VSS. 2. Applies to standard-voltage pins. 3. Allowable output current means the maximum current that can flow from VCC to each I/O pin. 4. Applies to high-voltage pins. 5. Total allowable input current means the sum of current that can flow at one time from all I/O pins to VSS. 6. Total allowable output current means the sum of current that can flow from VCC to all I/O pins.
Rev. 3.00, 12/94, page 246 of 334
Table 14-3 DC Characteristics Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Input high voltage Applicable Symbol Pins VIH RES IRQ0 to IRQ5 SCK1, SCK2 SI1, SI2 EVENT, UD OSC1 Rating Test Conditions Min 0.8 VCC VCC = 2.7 to 5.5 V 0.9 VCC incl. subactive mode 0.7 VCC VCC = 2.7 to 5.5 V incl. subactive mode Typ -- -- -- Max VCC +0.3 VCC +0.3 VCC +0.3 VCC +0.3 VCC +0.3 VCC +0.3 V V V Unit V Notes
VCC -0.5 -- VCC = 2.7 to 5.5 V VCC -0.3 -- incl. subactive mode
P00 to P07 P10 to P16 P80 to P87 P90 to P97 PA0 to PA1 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P17 Input low voltage VIL RES, SCK1, SCK2 IRQ0 to IRQ5 SI1, SI2 EVENT, UD OSC1
VCC = 2.7 to 5.5 V 0.7 VCC incl. subactive mode
--
VCC = 2.7 to 5.5 V 0.7 VCC incl. subactive mode
--
VCC +0.3
V
-0.3 VCC = 2.7 to 5.5 V -0.3 incl. subactive mode VCC = 2.7 to 5.5 V -0.3 incl. subactive mode -0.3 VCC = 2.7 to 5.5 V -0.3 incl. subactive mode
-- -- -- -- -- --
0.2 VCC 0.1 VCC 0.3 VCC 0.5 0.3 0.3 VCC
V
V V
P01 to P07 P10 to P16 P80 to P87 P90 to P97 PA0 to PA1 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P17
VCC = 2.7 to 5.5 V -0.3 incl. subactive mode
V
VCC = 2.7 to 5.5 V VCC -40 incl. subactive mode
--
0.3 VCC
V
Note: TEST pin should be connected to VSS.
Rev. 3.00, 12/94, page 247 of 334
Table 14-3 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Applicable Symbol Pins P10 to P15 P80 to P87 P90 to P97 PWM, SO1, SO2 PA0, PA1 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70 to P77 Output low VOL voltage P10 to P15 P80 to P87 P90 to P97 PWM, SO1, SO2 PA0, PA1 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70 to P77 Input leakage current IIL RES Rating Test Conditions -IOH = 1.0 mA -IOH = 0.5 mA VCC = 2.7 to 5.5 V -IOH = 0.3 mA -IOH = 15 mA -IOH = 10 mA -IOH = 4 mA VCC = 2.7 to 5.5 V -IOH = 4 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA VCC = 2.7 to 5.5 V IOL = 0.5 mA Pull-down resistance 150 k; pull-down voltage VCC -40 V VIN = 0 to VCC Min Typ Max -- -- -- Unit V Notes
Output high VOH voltage
VCC -1.0 -- VCC -0.5 -- VCC -0.5 -- VCC -3.0 -- VCC -2.0 -- VCC -1.0 -- -- --
-- -- --
V
VCC -1.0 -- -- 0.4
V V
Reference value
--
0.4
--
V
Reference value
--
--
VCC -37
V
40
A
Rev. 3.00, 12/94, page 248 of 334
Table 14-3 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Applicable Symbol Pins TEST SCK1, SCK2 SI1, SI2 IRQ0 to IRQ5 EVENT, UD OSC1 P01 to P07 P10 to P16 P80 to P87 P90 to P97 PA0, PA1 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P17 Input capacitance CIN Input pins and I/O pins other than power source pin P16/EVENT RES Rating Test Conditions VIN = 0 to VCC Min -- Typ -- Max 1 Unit A Notes
I/O leakage IIL current
VIN = VCC -40 to VCC
--
--
20
A
f = 1 MHz, VIN = 0 V Ta = 25C
--
--
20
pF
-- --
-- --
35 70
Rev. 3.00, 12/94, page 249 of 334
Table 14-3 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Power dissipation when CPU operating in active mode Symbol IOPE Applicable Pins Test Conditions VCC VCC = 5 V, fOSC = 8 MHz VCC = 5 V, fOSC = 4 MHz VCC = 3 V, fOSC = 4 MHz Power dissipation during reset in active mode IRES VCC VCC = 5 V, fOSC = 8 MHz VCC = 5 V, fOSC = 4 MHz VCC = 3 V, fOSC = 4 MHz Power ISLEEP dissipation in sleep mode VCC VCC = 5 V, fOSC = 8 MHz VCC = 5 V, fOSC = 4 MHz VCC = 3 V, fOSC = 4 MHz Power ISUB dissipation in subactive mode VCC VCC = 2.7 V 32 kHz crystal oscillator used VCC = 5.0 V 32 kHz crystal oscillator used VCC VCC = 2.7 V 32 kHz crystal oscillator used VCC = 5.0 V 32 kHz crystal oscillator used Power dissipation in standby mode ISTBY VCC 32 kHz crystal oscillator not used X1 = VCC Rating Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ 17 9 6 6 3 1.5 2.5 1.5 1.0 6 11 16 22 3.2 3.8 10 12 -- Max -- -- -- 9 5 -- 3.5 2.0 -- 20 -- -- -- 6 -- -- -- 10 A A A A A A A A A 2 Reference value 2 2 Reference value 2 mA 1 mA 1 Unit mA Notes Reference value 1
Power IWATCH dissipation in watch mode
Rev. 3.00, 12/94, page 250 of 334
Table 14-3 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item RAM data retention voltage in standby mode Symbol VSTBY Applicable Pins Test Conditions VCC 32 kHz crystal oscillator not used X1 = VCC Rating Min 2 Typ -- Max -- Unit V Notes
Notes: 1. Does not include current flowing to output buffer. 2. Reference value when bypass capacitor of 47 F is connected between VCC and VSS.
Rev. 3.00, 12/94, page 251 of 334
14.2.2 HD6473724 and HD6473726 AC Characteristics Regarding the AC characteristics, Table 14-4 gives the control signal timing of HD6473724 and HD6473726, and Table 14-5 gives the serial interface timing. Table 14-4 Control Signal Timing Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Clock pulse generator frequency Clock cycle time Symbol fOSC Applicable Pins Test Conditions OSC1, OSC2, OSC1, OSC2, Rating Min 2 VCC = 2.7 to 5.5 V 2 119 VCC = 2.7 to 5.5 V 238 238 VCC = 2.7 to 5.5 V fx X1, X2 VCC = 2.7 to 5.5 V 476 -- Typ -- -- -- -- -- -- Max 8.4 4.2 500 500 1000 1000 kHz ns ns Figure 14-1 Unit MHz Reference Diagram
tCYC
Instruction cycle time Subclock pulse generator frequency Subclock cycle time Subactive instruction cycle time Oscillator settling time (crystal oscillator) Oscillator settling time (ceramic oscillator) Oscillator settling time External clock pulse width (high) External clock pulse width (low) External clock rise time External clock fall time
32.768 --
tsubcyc SUB
X1, X2
VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V
-- --
30.5
--
s s
244.14 --
trc
OSC1, OSC2, OSC1, OSC2, X1, X2 OSC1
-- VCC = 2.7 to 5.5 V -- -- VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V -- -- 40 VCC = 2.7 to 5.5 V 100 40 VCC = 2.7 to 5.5 V 100 -- VCC = 2.7 to 5.5 V -- -- VCC = 2.7 to 5.5 V --
-- -- -- -- -- -- -- -- -- -- -- -- --
40 60 20 40 2 -- -- -- -- 20 20 20 20
ms
trc
ms
trc tCPH tCPL tCPr tCPf
s ns Figure 14-1
OSC1 OSC1 OSC1
ns
ns
ns
Rev. 3.00, 12/94, page 252 of 334
Table 14-4 Control Signal Timing (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item RES pin pulse width (low) IRQ pin pulse width (high) IRQ pin pulse width (low) EVENT pin pulse width (high) EVENT pin pulse width (low) UD pin minimum change width Symbol tREL tIH tIL tEVH tEVL tUDH tUDL Applicable Pins Test Conditions RES IRQ0 to IRQ5 IRQ0 to IRQ5 EVENT EVENT UD VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V Rating Min 10 2 2 2 2 2 Typ -- -- -- -- -- -- Max -- -- -- -- -- -- Unit SUB SUB Figure 14-5 Figure 14-4 Reference Diagram Figure 14-2 Figure 14-3
Table 14-5 Serial Interface Timing Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Output transfer clock cycle time Output transfer clock pulse width (high) Output transfer clock pulse width (low) Output transfer clock rise time Output transfer clock fall time Input transfer clock cycle time Input transfer clock pulse width (high) Symbol tscyc tSCKH Applicable Pins Test Conditions SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V Rating Min 2 0.4 Typ -- -- Max -- -- Unit tscyc Reference Diagram Figure 14-6
tSCKL
VCC = 2.7 to 5.5 V
0.4
--
--
tscyc
tSCKr tSCKf tscyc tSCKH
-- VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V -- -- -- 1 0.4
-- -- -- -- -- --
60 80 60 80 -- --
ns
ns tscyc
Rev. 3.00, 12/94, page 253 of 334
Table 14-5 Serial Interface Timing (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Input transfer clock pulse width (low) Input transfer clock rise time Input transfer clock fall time Serial output data delay time Serial input data setup time Serial input data hold time Transfer hold time Symbol tSCKL Applicable Pins Test Conditions SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SO1, SO2 VCC = 2.7 to 5.5 V tsSI thSI tSCK2 SI1, SI2 VCC = 2.7 to 5.5 V SI1, SI2 VCC = 2.7 to 5.5 V SCK2 When pin SCK2 is input pin When pin SCK2 is input pin VCC = 2.7 to 5.5 V When pin SCK2 is output pin VCC = 2.7 to 5.5 V Transfer end acknowledge time tCS CS VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V Rating Min 0.4 Typ -- Max -- Unit tscyc Reference Diagram Figure 14-6
tSCKr tSCKf tdSO
-- VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V -- -- -- -- -- 230 470 230 470 0.2 0.4
-- -- -- -- -- -- -- -- -- -- -- --
60 80 60 80 200 350 -- -- -- -- 40 40
ns
ns
ns
ns
ns
s
Figure 14-7
--
--
1
tscyc
3
--
4
Rev. 3.00, 12/94, page 254 of 334
14.2.3 HD6473724 and HD6473726 A/D Converter Characteristics Table 14-6 gives the HD6473724 and HD6473726 A/D converter characteristics. Table 14-6 A/D Converter Characteristics Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Analog supply voltage Analog input voltage Analog current Symbol AVCC Applicable Pins AVCC Rating Test Conditions Min VCC -0.3 Typ VCC Max VCC +0.3 Unit V Notes
AVIN AICC AISTOP CAIN
AN0 to AN7 AVCC AVCC = 5 V Reset and powerdown mode AN0 to AN7 AN0 to AN7
AVSS -- -- -- --
-- -- -- -- --
AVCC 200 10 30 10
V A A pF k
Analog input capacitance
Allowable RAIN signal source impedance Resolution Absolute precision
-- VCC = AVCC = 5 V VCC = AVCC = 4.0 to 5.5 V -- -- 31
-- -- 2.5 15.5
8 2.5 -- 14.8
Bit LSB Reference value s
Conversion time
Rev. 3.00, 12/94, page 255 of 334
14.3 HD6433723, HD6433724, HD6433725, HD6433726, HD6433753, and HD6433754 Electrical Characteristics
14.3.1 HD6433723, HD6433724, HD6433725, HD6433726, HD6433753, and HD6433754 DC Characteristics
Table 14-7 gives the allowable current values of the HD6433723, HD6433724, HD6433725, HD6433726, HD6433753, and HD6433754, and table 14-8 gives the electrical characteristics. Table 14-7 Allowable Current Sink Values Conditions: VCC = 4.0 to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C
Item Allowable input current (into LSI) Allowable output current (from LSI) Allowable output current (from LSI) Total allowable input current (into LSI) Total allowable output current (from LSI) Total allowable output current to Vdisp Symbol IO -IO -IO IO -IO -IO Rating 2 2 20 50 150 30 Unit mA mA mA mA mA mA Notes 1, 2 2, 3 3, 4 5 6 7
Notes: 1. Allowable input current means the maximum current that can flow from each I/O pin to VSS. 2. Applies to standard-voltage pins. 3. Allowable output current means the maximum current that can flow from VCC to each I/O pin. 4. Applies to high-voltage pins. 5. Total allowable input current means the sum of current that can flow at one time from all I/O pins to VSS. 6. Total allowable output current means the sum of current that can flow from VCC to all I/O pins. 7. Total allowable output current to Vdisp is the sum of current that can flow from all I/O pins to Vdisp.
Rev. 3.00, 12/94, page 256 of 334
Table 14-8 DC Characteristics Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Input high voltage Applicable Symbol Pins VIH RES IRQ0 to IRQ5 SCK1, SCK2 SI1, SI2 EVENT, UD OSC1 Rating Test Conditions Min 0.8 VCC VCC = 2.5 to 5.5 V 0.9 VCC incl. subactive mode 0.7 VCC VCC = 2.5 to 5.5 V incl. subactive mode Typ -- -- -- Max VCC +0.3 VCC +0.3 VCC +0.3 VCC +0.3 VCC +0.3 VCC +0.3 V V V Unit V Notes
VCC -0.5 -- VCC = 2.5 to 5.5 V VCC -0.3 -- incl. subactive mode
P00 to P07 P10 to P16 P80 to P87 P90 to P97 PA0, PA1 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P17 Input low voltage VIL RES, SCK1, SCK2 IRQ0 to IRQ5 SI1, SI2 EVENT, UD OSC1
VCC = 2.5 to 5.5 V 0.7 VCC incl. subactive mode
--
VCC = 2.5 to 5.5 V 0.7 VCC incl. subactive mode
--
VCC +0.3
V
-0.3 VCC = 2.5 to 5.5 V -0.3 incl. subactive mode VCC = 2.5 to 5.5 V -0.3 incl. subactive mode -0.3 VCC = 2.5 to 5.5 V -0.3 incl. subactive mode
-- -- -- -- -- --
0.2 VCC 0.1 VCC 0.3 VCC 0.5 0.3 0.3 VCC
V
V V
P01 to P07 P10 to P16 P80 to P87 P90 to P97 PA0, PA1 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P17
VCC = 2.5 to 5.5 V -0.3 incl. subactive mode
V
VCC = 2.5 to 5.5 V VCC -40 incl. subactive mode
--
0.3 VCC
V
Note: TEST pin should be connected to VSS.
Rev. 3.00, 12/94, page 257 of 334
Table 14-8 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Applicable Symbol Pins P10 to P15 P80 to P87 P90 to P97 PWM, SO1, SO2 PA0, PA1 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70 to P77 Output low VOL voltage P10 to P15 P80 to P87 P90 to P97 PWM, SO1, SO2 PA0, PA1 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70 to P77 Rating Test Conditions -IOH = 1.0 mA -IOH = 0.5 mA VCC = 2.7 to 5.5 V -IOH = 0.3 mA -IOH = 15 mA -IOH = 10 mA -IOH = 4 mA VCC = 2.7 to 5.5 V -IOH = 4 mA VCC = 4.0 to 5.5 V IOL = 1.6 mA VCC = 2.7 to 5.5 V IOL = 0.5 mA Vdisp = VCC -40 V Min Typ Max -- -- -- Unit V Notes
Output high VOH voltage
VCC -1.0 -- VCC -0.5 -- VCC -0.5 -- VCC -3.0 -- VCC -2.0 -- VCC -1.0 -- -- --
-- -- --
V
VCC -1.0 -- -- 0.4
V V
Reference value
--
0.4
--
V
Reference value With pull-down MOS
--
--
VCC -37
V
Pull-down resistance 150 k; pull-down voltage VCC -40 V Mask ROM version: VIN = 0 to VCC
--
--
VCC -37
Input leakage current
IIL
RES
--
--
1
A
Rev. 3.00, 12/94, page 258 of 334
Table 14-8 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Applicable Symbol Pins TEST SCK1, SCK2 SI1, SI2 IRQ0 to IRQ5 EVENT, UD OSC1 P01 to P07 P10 to P16 P80 to P87 P90 to P97 PA0, PA1 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P17 Pull-up MOS current Pull-down MOS current -Ip P10 to P16 P80 to P87 P90 to P97 PA0, PA1 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70 to P77 Input pins other than power source pin P17 Rating Test Conditions VIN = 0 to VCC Min -- Typ -- Max 1 Unit A Notes
I/O leakage IIL current
VIN = VCC -40 to VCC
--
--
20
A
Not including pins with pull-down MOS
VCC = 5 V, VIN = 0 V VCC = 2.7 V, VIN = 0 V Vdisp = VCC -36 VIN = VCC Vdisp = VCC -18 VIN = VCC f = 1 MHz, VIN = 0 V Ta = 25C
50 -- 120
-- 25 --
300 -- 800
A Reference value A
Id
-- --
280 --
-- 15 pF
Reference value
Input capacitance
CIN
--
--
30
Rev. 3.00, 12/94, page 259 of 334
Table 14-8 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Power dissipation when CPU operating in active mode Symbol IOPE Applicable Test Conditions Pins VCC VCC = 5 V, fOSC = 8 MHZ VCC = 5 V, fOSC = 4 MHz VCC = 3 V, fOSC = 4 MHz Power dissipation during reset in active mode IRES VCC VCC = 5 V, fOSC = 8 MHz VCC = 5 V, fOSC = 4 MHz VCC = 3 V, fOSC = 4 MHz ISLEEP Power dissipation in sleep mode VCC VCC = 5 V, fOSC = 8 MHz VCC = 5 V, fOSC = 4 MHz VCC = 3 V, fOSC = 4 MHz ISUB Power dissipation in subactive mode VCC VCC = 2.5 V 32 kHz crystal oscillator used VCC = 5.0 V 32 kHz crystal oscillator used IWATCH Power dissipation in watch mode VCC VCC = 2.5 V 32 kHz crystal oscillator used VCC = 5.0 V 32 kHz crystal oscillator used Power dissipation in standby mode ISTBY VCC 32 kHz crystal oscillator not used X1 = VCC Rating Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ 15 8 5 5 2.5 1.3 2 1 0.6 5 9 13 20 2.2 2.8 6 8 -- Max -- -- -- 8 4 -- 3 1.5 -- 20 -- -- -- 5 -- -- -- 5 A A A A A A A A A 2 Reference value 2 2 Reference value 2 mA 1 mA 1 Unit mA Notes Reference value 1
Rev. 3.00, 12/94, page 260 of 334
Table 14-8 DC Characteristics (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item RAM data retention voltage in standby mode Symbol VSTBY Applicable Pins Test Conditions VCC 32 kHz crystal oscillator not used X1 = VCC Rating Min 2 Typ -- Max -- Unit V Notes
Notes: 1. Does not include current flowing to pull-up MOS or output buffer. 2. Reference value when bypass capacitor of 47 F is connected between VCC and VSS.
Rev. 3.00, 12/94, page 261 of 334
14.3.2 HD6433723, HD6433724, HD6433725, HD6433726, HD6433753, and HD6433754 AC Characteristics As for the AC characteristics, Table 14-9 gives the control signal timing of HD6433723, HD6433724, HD6433725, HD6433726, HD6433753, and HD6433754 while Table 14-10 gives the serial interface timing. Table 14-9 Control Signal Timing Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Clock pulse generator frequency Clock cycle time Symbol fOSC Applicable Test Conditions Pins OSC1, OSC2, OSC1, OSC2, VCC = 2.7 to 5.5 V Rating Min 2 2 119 VCC = 2.7 to 5.5 V 238 238 VCC = 2.7 to 5.5 V fx X1, X2 VCC = 2.5 to 5.5 V 476 -- Typ -- -- -- -- -- -- Max 8.4 4.2 500 500 1000 1000 kHz ns ns Figure 14-1 Unit MHz Reference Diagram
tCYC
Instruction cycle time Subclock pulse generator frequency Subclock cycle time Subactive instruction cycle time Oscillator settling time (crystal oscillator) Oscillator settling time (ceramic oscillator) Oscillator settling time External clock pulse width (high) External clock pulse width (low) External clock rise time External clock fall time
32.768 --
tsubcyc SUB
X1, X2
VCC = 2.5 to 5.5 V VCC = 2.5 to 5.5 V
-- --
30.5
--
s s
244.14 --
trc
OSC1, OSC2, OSC1, OSC2, X1, X2 OSC1
-- VCC = 2.7 to 5.5 V -- -- VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V -- -- 40 VCC = 2.7 to 5.5 V 100 40 VCC = 2.7 to 5.5 V 100 -- VCC = 2.7 to 5.5 V -- -- VCC = 2.7 to 5.5 V --
-- -- -- -- -- -- -- -- -- -- -- -- --
40 60 20 40 2 -- -- -- -- 20 20 20 20
ms
trc
ms
trc tCPH tCPL tCPr tCPf
s ns ns ns ns Figure 14-1
OSC1 OSC1 OSC1
Rev. 3.00, 12/94, page 262 of 334
Table 14-9 Control Signal Timing (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item RES pin pulse width (low) IRQ pin pulse width (high) IRQ pin pulse width (low) EVENT pin pulse width (high) EVENT pin pulse width (low) UD pin minimum change width Symbol tREL tIH tIL tEVH tEVL tUDH tUDL Applicable Pins Test Conditions RES IRQ0 to IRQ5 IRQ0 to IRQ5 EVENT EVENT UD VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V Rating Min 10 2 2 2 2 2 Typ -- -- -- -- -- -- Max -- -- -- -- -- -- Unit SUB SUB Figure 14-5 Figure 14-4 Reference Diagram Figure 14-2 Figure 14-3
Table 14-10 Serial Interface Timing Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Output transfer clock cycle timing Output transfer clock pulse width (high) Output transfer clock pulse width (low) Output transfer clock rise time Output transfer clock fall time Input transfer clock cycle timing Input transfer clock pulse width (high) Symbol tscyc tSCKH Applicable Pins Test Conditions SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V Rating Min 2 0.4 Typ -- -- Max -- -- Unit tscyc Reference Diagram Figure 14-6
tSCKL
VCC = 2.7 to 5.5 V
0.4
--
--
tscyc
tSCKr tSCKf tscyc tSCKH
-- VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V -- -- -- 1 0.4
-- -- -- -- -- --
60 80 60 80 -- --
ns
ns tscyc
Rev. 3.00, 12/94, page 263 of 334
Table 14-10 Serial Interface Timing (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Item Input transfer clock pulse width (low) Input transfer clock rise time Input transfer clock fall time Serial output data delay time Serial input data setup time Serial input data hold time Transfer hold time Symbol tSCKL Applicable Pins Test Conditions SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SO1, SO2 VCC = 2.7 to 5.5 V tsSI thSI tSCK2 SI1, SI2 VCC = 2.7 to 5.5 V SI1, SI2 VCC = 2.7 to 5.5 V SCK2 When pin SCK2 is input pin When pin SCK2 is input pin VCC = 2.7 to 5.5 V When pin SCK2 is output pin VCC = 2.7 to 5.5 V Transfer end acknowledge time tCS CS VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V Rating Min 0.4 Typ -- Max -- Unit tscyc Reference Diagram Figure 14-6
tSCKr tSCKf tdSO
-- VCC = 2.7 to 5.5 V VCC = 2.7 to 5.5 V -- -- -- -- -- 230 470 230 470 0.2 0.4
-- -- -- -- -- -- -- -- -- -- -- --
60 80 60 80 200 350 -- -- -- -- 40 40
ns
ns
ns
ns
ns
s
Figure 14-7
--
--
1
tscyc
3
--
4
Rev. 3.00, 12/94, page 264 of 334
14.3.3 HD6433723, HD6433724, HD6433725, HD6433726, HD6433753, and HD6433754 A/D Converter Characteristics Table 14-11 gives the HD6433723, HD6433724, HD6433725, HD6433726, HD6433753, and HD6433754 A/D converter characteristics. Table 14-11 A/D Converter Characteristics (provisional values) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC - 40 to VCC, VSS = 0.0 V, Ta = -20 to +75C
Applicable Pins AVCC Rating Test Conditions Min VCC -0.3 Typ VCC Max VCC +0.3 Unit V Notes
Item Analog supply voltage Analog input voltage Analog current
Symbol AVCC
AVIN AICC AISTOP CAIN
AN0 to AN7 AVCC AVCC = 5 V Reset and powerdown mode AN0 to AN7 AN0 to AN7
AVSS -- -- -- --
-- -- -- -- --
AVCC 200 10 30 10
V A A pF k
Analog input capacitance
Allowable RAIN signal source impedance Resolution Absolute precision
-- VCC = AVCC = 5 V VCC = AVCC = 4.0 to 5.5 V -- -- 31
-- -- 2.5 15.5
8 2.5 -- 14.8
Bit LSB Reference value S
Conversion time
Rev. 3.00, 12/94, page 265 of 334
14.4 Operational Timing
This section provides the following timing charts (figures 14-1 to 14-8).
tcyc OSC1 VIH VIL tCPH tCPr tCPf tCPL
Figure 14-1 System Clock Input Timing
RES
VIL tREL
Figure 14-2 RES Pin Pulse Width (low)
IRQ0 to IRQ5
VIH VIL tIL tIH
Figure 14-3 IRQ Pin Input Timing
EVENT
VIH VIL tEVL tEVH
Figure 14-4 EVENT Pin Minimum Pulse Width
Rev. 3.00, 12/94, page 266 of 334
UD
VIH VIL tUDL tUDH
Figure 14-5 UD Pin Minimum Change Width
tscyc
SCK1 SCK2
VIH or VOH* VIL or VOL* tSCKf tSCKL tdso tSCKr tSCKH
SO1 SO2
VOH* VOL* tssi thsi
SI1 SI2
Note: * Output timing reference levels: Output high level: VOH: 2.0 V Output low level: VOL: 0.8 V See figure 14-8 for the load conditions.
Figure 14-6 SCI I/O Timing
Rev. 3.00, 12/94, page 267 of 334
VOH* CS VOL*
tSCK2
tCS
SCK2
VIH or VOL* VIL or VOL* Note: * Output timing reference levels: Output high level: VOH: 2.0 V Output low level: VOL: 0.8 V See figure 14-8 for the load conditions.
Figure 14-7 Serial Communication Interface 2 Chip Select Timing
VCC 2.4 k LSI output pin 30 pF 12 k
Figure 14-8 Output Load Conditions
Rev. 3.00, 12/94, page 268 of 334
14.5 Differences in Electrical Characteristics between Mask ROM and ZTATTM Versions
Table 14-12 shows the difference in electrical characteristics between mask ROM and ZTATTM versions. Table 14-12 Differences in Electrical Characteristics between Mask ROM and ZTATTM Versions
Applicable Pins VCC Mask ROM Version ZTATTM Version Test Conditions Min 2.5 Typ -- Max 5.5 Min 2.7 Typ -- Max Unit 5.5 V
Item Operation range in subactive mode
Symbol
Input leakage IIL current Input capacitance Power dissipation when CPU operating in active mode CIN
RES P16/EVENT P17/Vdisp RES
-- -- -- -- VCC = 5 V, fOSC = 8 MHz VCC = 5 V, fOSC = 4 MHz VCC = 3 V, fOSC = 4 MHz -- -- -- -- -- -- -- -- --
-- -- -- -- 15 8 5 5 2.5 1.3 2 1 0.6
1 15 30 15 -- -- -- 8 4 -- 3 1.5 --
-- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- 17 9 6 6 3 1.5 2.5 1.5 1
40 35 20 70 -- -- -- 9 5 -- 3.5 2 --
A pF
IOPE
VCC
mA
Power dissipation during reset in active mode
IRES
VCC
VCC = 5 V, fOSC = 8 MHz VCC = 5 V, fOSC = 4 MHz VCC = 3 V, fOSC = 4 MHz
mA
Power dissipation in sleep mode
ISLEEP
VCC
VCC = 5 V, fOSC = 8 MHz VCC = 5 V, fOSC = 4 MHz VCC = 3 V, fOSC = 4 MHz
Rev. 3.00, 12/94, page 269 of 334
Table 14-12
Differences in Electrical Characteristics between Mask ROM and ZTATTM Versions (cont)
Applicable Pins VCC Mask ROM Version ZTATTM Version Test Conditions VCC = 2.5 V (no bypass capacitor) VCC = 2.5 V (47 F bypass capacitor) VCC = 2.7 V (no bypass capacitor) VCC = 2.7 V (47 F bypass capacitor) VCC = 5 V (no bypass capacitor) VCC = 5 V (47 F bypass capacitor) -- -- 13 20 -- -- Min -- -- Typ 5 9 Max 20 -- Min Typ Max Unit A
Item Power dissipation in subactive mode
Symbol ISUB
-- --
6 11
20 --
-- --
16 22
-- --
Power dissipation in watch mode
IWATCH
VCC
VCC = 2.5 V (no bypass capacitor) VCC = 2.5 V (47 F bypass capacitor) VCC = 2.7 V (no bypass capacitor) VCC = 2.7 V (47 F bypass capacitor) VCC = 5 V (no bypass capacitor) VCC = 5 V (47 F bypass capacitor)
-- --
2.2 2.8
5 --
-- --
3.2 3.8
6 --
A
-- --
6 8
-- --
-- --
10 12
-- --
Power P dissipation in standby mode
ISTBY
VCC
--
--
5
--
--
10
A
Rev. 3.00, 12/94, page 270 of 334
Appendix A CPU Instruction Set
A.1 Instruction Set List
Operation Notation
Rd8/16 Rs8/16 Rn8/16 CCR N Z V C PC SP #xx:3/8/16 d:8/16 @aa:8/16 + - x / -- General register (destination) (8 or 16 bits) General register (source) (8 or 16 bits) General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data (3, 8, or 16 bits) Displacement (8 or 16 bits) Absolute address (8 or 16 bits) Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Inverse logic
Condition Code Notation Symbol
* 0 -- Modified according to the instruction result Not fixed (value not guaranteed) Always cleared to 0 Not affected by the instruction execution result
Rev. 3.00, 12/94, page 271 of 334
A.2 Operation Code Map
Table A-1 is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Some pairs of instructions have identical first bytes. These instructions are differentiated by the first bit of the second byte (bit 7 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
Rev. 3.00, 12/94, page 272 of 334
Table A-1 Operation Code Map
LO 2 LDC ORC NOT OR ROTR NEG XOR AND SUB DEC SUBS CMP XORC ANDC LDC ADD INC ADDS MOV ROTXR ADDX 3 4 5 6 7 8 9 A B C D E
HI
0
1
F
0
NOP
SLEEP
STC
DAA
SHLL
SHLR
ROTXL
1
SUBX
DAS
SHAL
SHAR
ROTL
2 MOV
3 BLS BCC RTS BST BSR RTE JMP BCS BNE BEQ BVC BVS BPL BMI
4
BRA
BRN
BHI
BGE
BLT
BGT
BLE
5
MULXU
DIVXU
JSR
6 BTST BOR MOV BIOR ADD BIXOR BIAND BILD BXOR BAND BIST BLD
MOV *
BSET
BNOT
BCLR
7
EEPMOV
Bit manipulation instruction
8 ADDX
9 CMP
A
B
SUBX
C
OR
D
XOR
E
AND
F
MOV
Rev. 3.00, 12/94, page 273 of 334
Note: * The PUSH and POP instructions are identical in machine language to MOV instructions.
;
A.3 Number of States Required for Execution
Table A-2 Instruction Set
Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC)
@aa:8/16
#xx:8/16
@@aa
@Rn
Condition Code -- IHNZVC ---- ----
Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @--Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd
Operation
B #xx:8 Rd8 B Rs8 Rd8 B @Rs16 Rd8 B @(d:16, Rs16) Rd8 B @Rs16 Rd8 Rs16+1 Rs16 B @aa:8 Rd8 B @aa:16 Rd8 B Rs8 @Rd16 B Rs8 @(d:16, Rd16) B Rd16-1 Rd16 Rs8 @Rd16 B Rs8 @aa:8 B Rs8 @aa:16 W #xx:16 Rd W Rs16 Rd16 W @Rs16 Rd16 W @Rs16 Rd16 Rs16+2 Rs16 W @aa:16 Rd16 W Rs16 @Rd16 W Rd16-2 Rd16 Rs16 @Rd16 W Rs16 @aa:16 W @SP Rd16 SP+2 SP W SP-2 SP Rs16 @SP
Rn
2 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2 2
0--2 0--2 0--4 0--6 0--6 0--4 0--6 0--4 0--6 0--6 0--4 0--6 0--4 0--2 0--4 0--6 0--6 0--6 0--4 0--6 0--6 0--6 0--6 0--6
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) Rd16 MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd
MOV.W Rs, @(d:16, Rd) W Rs16 @(d:16, Rd16) MOV.W Rs, @--Rd MOV.W Rs, @aa:16 POP Rd PUSH Rs
Rev. 3.00, 12/94, page 274 of 334
Table A-2 Instruction Set (cont)
Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC)
@aa:8/16
#xx:8/16
@@aa
@Rn
Condition Code -- IHNZVC
Mnemonic EEPMOV
Operation
Rn
-- if R4L0 then Repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L Until R4L=0 else next B Rd8+#xx:8 Rd8 B Rd8+Rs8 Rd8 W Rd16+Rs16 Rd16 B Rd8+#xx:8 +C Rd8 B Rd8+Rs8 +C Rd8 W Rd16+1 Rd16 W Rd16+2 Rd16 B Rd8+1 Rd8 B Rd8 decimal adjust Rd8 B Rd8-Rs8 Rd8 W Rd16-Rs16 Rd16 B Rd8-#xx:8-C Rd8 B Rd8-Rs8-C Rd8 W Rd16-1 Rd16 W Rd16-2 Rd16 B Rd8-1 Rd8 B Rd8 decimal adjust Rd8 B 0-Rd Rd B Rd8-#xx:8 B Rd8-Rs8 W Rd16-Rs16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
4 ------------
ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.W #1, Rd ADDS.W #2, Rd INC.B Rd DAA.B Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.W #1, Rd SUBS.W #2, Rd DEC.B Rd DAS.B Rd NEG.B Rd CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd
-- -- -- --

2 2 2 2 2
--

------------ 2 ------------ 2 ---- --* -- -- -- --2 *2 2 2 2 2
--

------------ 2 ------------ 2 ---- --* -- -- -- --2 *--2 2 2 2 2
--
Rev. 3.00, 12/94, page 275 of 334
Table A-2 Instruction Set (cont)
Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC)
@aa:8/16
#xx:8/16
@@aa
MULXU.B Rs, Rd DIVXU.B Rs, Rd
B Rd8 x Rs8 Rd16 B Rd16/Rs8 Rd16 (RdH: remainder, RdL: quotient) B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd Rd B C b7 b0 C b7 b0 0 b7 b0 C b7 b0 0 2 2 2
2 2
--
Mnemonic
Operation
@Rn
Condition Code IHNZVC
Rn
-- -- -- -- -- -- 14 -- -- -- -- 14
AND.B #xx:8, Rd AND.B Rs, Rd OR.B #xx:8, Rd OR.B Rs, Rd XOR.B #xx:8, Rd XOR.B Rs, Rd NOT.B Rd SHAL.B Rd
---- 2 ---- ---- 2 ---- ---- 2 2 2 ---- ---- ----
0--2 0--2 0--2 0--2 0--2 0--2 0--2 2
SHAR.B Rd
B
2
----
02
SHLL.B Rd
B
C
2
----
02
SHLR.B Rd
B
0
2
---- 0 0 2
ROTXL.B Rd
B
C b7 b0
2
----
02
ROTXR.B Rd
B b7 b0 C
2
----
02
Rev. 3.00, 12/94, page 276 of 334
Table A-2 Instruction Set (cont)
Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC)
@aa:8/16
#xx:8/16
@@aa
--
Mnemonic ROTL.B Rd
Operation C b7 b0
@Rn
Condition Code IHNZVC ----
Rn
B
2
02
ROTR.B Rd
B C b7 b0
2
----
02
BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8 BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8
B (#xx:3 of Rd8) 1 B (#xx:3 of @Rd16) 1 B (#xx:3 of @aa:8) 1 B (Rn8 of Rd8) 1 B (Rn8 of @Rd16) 1 B (Rn8 of @aa:8) 1 B (#xx:3 of Rd8) 0 B (#xx:3 of @Rd16) 0 B (#xx:3 of @aa:8) 0 B (Rn8 of Rd8) 0 B (Rn8 of @Rd16) 0 B (Rn8 of @aa:8) 0 B (#xx:3 of Rd8) (#xx:3 of Rd8) B (#xx:3 of @Rd16) (#xx:3 of @Rd16) B (#xx:3 of @aa:8) (#xx:3 of @aa:8) B (Rn8 of Rd8) (Rn8 of Rd8) B (Rn8 of @Rd16) (Rn8 of @Rd16) B (Rn8 of @aa:8) (Rn8 of @aa:8)
2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4
------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8
Rev. 3.00, 12/94, page 277 of 334
Table A-2 Instruction Set (cont)
Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC)
@aa:8/16
#xx:8/16
@@aa
BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @Rd
B (#xx:3 of Rd8) Z B (#xx:3 of @Rd16) Z B (#xx:3 of @aa:8) Z B (Rn8 of Rd8) Z B (Rn8 of @Rd16) Z B (Rn8 of @aa:8) Z B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C
--
Mnemonic
Operation
@Rn
Condition Code IHNZVC
Rn
2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4
------ ---- 2 ------ ---- 6 ------ ---- 6 ------ ---- 2 ------ ---- 6 ------ ---- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6
Rev. 3.00, 12/94, page 278 of 334
Table A-2 Instruction Set (cont)
Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC)
@aa:8/16
#xx:8/16
@@aa
BIOR #xx:3, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 JMP @Rn JMP @aa:16 JMP @@aa:8 BSR d:8
B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C -- PC PC+d:8 -- PC PC+2 -- If condition is true -- then -- PC PC+d:8 -- else next; -- -- -- -- -- -- -- -- -- -- -- PC Rn16 -- PC aa:16 -- PC @aa:8 -- SP-2 SP PC @SP PC PC+d:8 CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV = 0 NV = 1 Z (NV) = 0 Z (NV) = 1 2 2 4 2 4
--
Mnemonic
Operation
Rn
Branching Condition
@Rn
Condition Code IHNZVC
4
---------- 6 ---------- 2 ---------- 6
4
---------- 6 ---------- 2 ---------- 6
4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
---------- 6 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4
4 2 2
------------ 6 ------------ 8 ------------ 6
Rev. 3.00, 12/94, page 279 of 334
Table A-2 Instruction Set (cont)
Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC)
@aa:8/16
#xx:8/16
@@aa
JSR @Rn
-- SP-2 SP PC @SP PC Rn16 -- SP-2 SP PC @SP PC aa:16 SP-2 SP PC @SP PC @aa:8 -- PC @SP SP+2 SP -- CCR @SP SP+2 SP PC @SP SP+2 SP -- Transit to sleep mode. B #xx:8 CCR B Rs8 CCR B CCR Rd8 B CCR#xx:8 CCR B CCR#xx:8 CCR B CCR#xx:8 CCR -- PC PC+2 2 2 2 2 2 2
2
--
Mnemonic
Operation
@Rn
Condition Code IHNZVC
Rn
------------ 6
JSR @aa:16
4
------------ 8
JSR @@aa:8
2
------------ 8
RTS RTE
2 ------------ 8 2 10
SLEEP LDC #xx:8, CCR LDC Rs, CCR STC CCR, Rd ANDC #xx:8, CCR ORC #xx:8, CCR XORC #xx:8, CCR NOP Notes:
2 ------------ 2 2 2 2 2 2
------------ 2
2 ------------ 2
Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. Set to 1 if decimal adjustment produces a carry; otherwise cleared to 0. The number of states required for execution is 4n+9 (n = value of R4L). Set to 1 if the divisor is negative; otherwise cleared to 0. Set to 1 if the divisor is zero; otherwise cleared to 0.
Rev. 3.00, 12/94, page 280 of 334
Appendix B I/O Register Field
B.1 I/O Register Fields (1)
Addr. (Last Register Byte) Name H'A0 STAR H'A1 EDAR H'A2 SCR2 H'A3 STSR Bit Names Bit 7 -- -- -- -- Bit 6 -- -- -- -- Bit 5 -- -- -- -- Bit 4 STA4 EDA4 I/O SO2 LAST BIT Bit 3 STA3 EDA3 GAP2 OVR Bit 2 STA2 EDA2 GAP1 WT Bit 1 STA1 EDA1 PS1 GIT Bit 0 STA0 EDA0 PS0 STF Module Name SCI2
H'A4 -- to H'AF H'B0 SMR1 H'B1 SDRU1 H'B2 SDRL1 H'B3 SPR1 -- SMR16 SMR15
Not used
--
SMR14
SMR13
SMR12
SMR11
SMR10
SCI1
SDRU17 SDRU16 SDRU15 SDRU14 SDRU13 SDRU12 SDRU11 SDRU10 SDRL17 SDRL16 SDRL15 SDRL14 SDRL13 SDRL12 SDRL11 SDRL10 SO1 LAST BIT -- -- -- -- -- VFLAG FLMO VFDE AMR7 ADR7 ADSF -- -- -- -- -- -- -- --
H'B4 -- H'B5 -- H'B6 -- H'B7 -- H'B8 -- H'B9 VFSR H'BA VFDR H'BB DBR H'BC AMR H'BD ADRR H'BE ADSR H'BF --
-- -- -- -- -- KSE DM2 DISP -- ADR6 -- --
-- -- -- -- -- -- DM1 -- -- ADR5 -- --
-- -- -- -- -- SR4 DM0 -- -- ADR4 -- --
-- -- -- -- -- SR3 DR3 DBR3 -- ADR3 -- --
-- -- -- -- -- SR2 DR2 DBR2 AMR2 ADR2 -- --
-- -- -- -- -- SR1 DR1 DBR1 AMR1 ADR1 -- --
-- -- -- -- -- SR0 DR0 DBR0 AMR0 ADR0 -- --
--
VFD controller/ driver A/D converter
Notation: SCI1: Serial communication interface 1 SCI2: Serial communication interface 2
Rev. 3.00, 12/94, page 281 of 334
B.1 I/O Register Fields (1) (cont)
Addr. (Last Register Byte) Name H'C0 TMA H'C1 TCA H'C2 TMB H'C3 TLB/TCB H'C4 TMC H'C5 TLC/TCC H'C6 TMD H'C7 TCD H'C8 TME H'C9 TLE/TCE H'CA -- H'CB -- H'CC PWCR H'CD PWDRU H'CE PWDRL H'CF -- H'D0 PDR0 H'D1 PDR1 H'D2 -- H'D3 PDR3 H'D4 PDR4 H'D5 PDR5 H'D6 PDR6 H'D7 PDR7 H'D8 PDR8 H'D9 PDR9 H'DA PDRA H'DB -- H'DC -- H'DD -- H'DE -- H'DF -- Bit Names Bit 7 -- TCA7 TMB7 TLB7/ TCB7 TMC7 TLC7/ TCC7 CLR TCD7 TME7 TLE7/ TCE7 -- -- -- -- Bit 6 -- TCA6 -- TLB6/ TCB6 TMC6 TLC6/ TCC6 -- TCD6 -- TLE6/ TCE6 -- -- -- -- Bit 5 -- TCA5 -- TLB5/ TCB5 TMC5 TLC5/ TCC5 -- TCD5 -- TLE5/ TCE5 -- -- -- Bit 4 -- TCA4 -- TLB4/ TCB4 -- TLC4/ TCC4 -- TCD4 -- TLE4/ TCE4 -- -- -- Bit 3 TMA3 TCA3 -- TLB3/ TCB3 -- TLC3/ TCC3 -- TCD3 -- TLE3/ TCE3 -- -- -- Bit 2 TMA2 TCA2 TMB2 TLB2/ TCB2 TMC2 TLC2/ TCC2 -- TCD2 TME2 TLE2/ TCE2 -- -- -- Bit 1 TMA1 TCA1 TMB1 TLB1/ TCB1 TMC1 TLC1/ TCC1 -- TCD1 TME1 TLE1/ TCE1 -- -- -- Bit 0 TMA0 TCA0 TMB0 TLB0/ TCB0 TMC0 TLC0/ TCC0 EDG TCD0 TME0 TLE0/ TCE0 -- -- PWCR0 14-bit PWM Timer E Timer D Timer C Timer B Module Name Timer A
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 -- PDR07 -- -- -- PDR47 PDR57 PDR67 PDR77 PDR87 PDR97 -- -- -- -- -- -- -- PDR06 -- -- -- PDR46 PDR56 PDR66 PDR76 PDR86 PDR96 -- -- -- -- -- -- -- PDR05 PDR15 -- -- PDR45 PDR55 PDR65 PDR75 PDR85 PDR95 -- -- -- -- -- -- -- PDR04 PDR14 -- -- PDR44 PDR54 PDR64 PDR74 PDR84 PDR94 -- -- -- -- -- -- -- PDR03 PDR13 -- PDR33 PDR43 PDR53 PDR63 PDR73 PDR83 PDR93 -- -- -- -- -- -- -- PDR02 PDR12 -- PDR32 PDR42 PDR52 PDR62 PDR72 PDR82 PDR92 -- -- -- -- -- -- -- PDR01 PDR11 -- PDR31 PDR41 PDR51 PDR61 PDR71 PDR81 PDR91 PDRA1 -- -- -- -- -- -- PDR00 PDR10 -- PDR30 PDR40 PDR50 PDR60 PDR70 PDR80 PDR90 PDRA0 -- -- -- -- -- I/O ports
Rev. 3.00, 12/94, page 282 of 334
B.1 I/O Register Fields (1) (cont)
Addr. (Last Register Byte) Name H'E0 -- H'E1 PCR1 H'E2 -- H'E3 -- H'E4 -- H'E5 -- H'E6 -- H'E7 -- H'E8 PCR8 H'E9 PCR9 H'EA PCRA H'EB PMR1 H'EC PMR2 H'ED PMR3 H'EE PMR4 H'EF PMR0 H'F0 H'F1 H'F2 H'F3 H'F4 H'F5 H'F6 H'F7 H'F8 H'F9 H'FA SYSCR1 SYSCR2 IEGR IENR1 IENR2 IENR3 IRR1 IRR2 IRR3 -- -- Bit Names Bit 7 -- -- -- -- -- -- -- -- PCR87 PCR97 -- Bit 6 -- -- -- -- -- -- -- -- PCR86 PCR96 -- Bit 5 -- PCR15 -- -- -- -- -- -- PCR85 PCR95 -- IRQC5 SI2 CS Bit 4 -- PCR14 -- -- -- -- -- -- PCR84 PCR94 -- IRQC4 SCK2 -- VRFR AN4 STS0 -- IEG4 IEN4 IENTE -- IRRI4 IRRTE -- -- -- -- -- -- -- -- Bit 3 -- PCR13 -- -- -- -- -- -- PCR83 PCR93 -- IRQC3 SO1 SO1 PMOS -- AN3 LSON DTON -- IEN3 IENTD -- IRRI3 IRRTD -- -- -- -- -- -- -- -- Bit 2 -- PCR12 -- -- -- -- -- -- PCR82 PCR92 -- IRQC2 SI1 -- -- AN2 -- -- -- IEN2 IENTC -- IRRI2 IRRTC -- -- -- -- -- -- -- -- Bit 1 -- PCR11 -- -- -- -- -- -- PCR81 PCR91 PCRA1 IRQC1 SCK1 -- -- AN1 -- -- IEG1 IEN1 IENTB IENS2 IRRI1 IRRTB IRRS2 -- -- -- -- -- -- -- Bit 0 -- PCR10 -- -- -- -- -- -- PCR80 PCR90 PCRA0 IRQC0 PWM -- -- AN0 -- -- IEG0 IEN0 IENTA IENS1 IRRI0 IRRTA IRRS1 -- -- -- -- -- -- -- System control Module Name I/O ports
NOISE EVENT CANCEL UP/ DOWN -- TEO AN7 SSBY -- -- -- -- IENAD -- -- IRRAD -- -- -- -- -- -- -- SO2 SO2 PMOS
TEO ON FREQ AN6 STS2 -- -- -- -- IENKS -- -- IRRKS -- -- -- -- -- -- -- AN5 STS1 -- -- IEN5 IENDT -- IRRI5 IRRDT -- -- -- -- -- -- -- --
H'FB -- H'FC -- H'FD -- H'FE -- H'FF --
Rev. 3.00, 12/94, page 283 of 334
B.2 I/O Register Fields (2)
Register fields are explained on the following pages in the format below.
Register acronym Register name Address to which register is mapped Name of on-chip peripheral module
DBR--Digit Beginning Register
H'BB
VFD Controller
Bit numbers
Bit 7 VFDE Initial value Read/Write 0 R/W 6 DISP 0 R/W 5 -- 0 -- 4 -- 0 R/W 3 DBR3 0 R/W 2 DBR2 0 R/W 1 DBR1 0 R/W 0 DBR0 0 R/W
Initial bit values
Segment Pin Select 0 0 0 0 FD0 to FD7 Possible types of access R W Read only Write only 0 0 0 1 FD1 to FD7, FS7 0 0 1 0 FD2 to FD7, FS7 to FS6 0 0 1 1 FD3 to FD7, FS7 to FS5 0 1 0 0 FD4 to FD7, FS7 to FS4 0 1 0 1 FD5 to FD7, FS7 to FS3 0 1 1 0 FD6 to FD7, FS7 to FS2 0 1 1 1 FD to FD7, FS7 to FS1 1*** Display Bit 0 All segment pins are in non-illuminating state (pull-down state). Digit pins continue operating. Register and RAM values are unchanged. 1 Display RAM contents are output to segment pins. FS7 to FS0 Note: * Don't care.
Bit names and positions. Dashes (--) indicate reserved bits.
R/W Read and write
Full name of bit
Bit settings and descriptions
Rev. 3.00, 12/94, page 284 of 334
STAR--Start Address Register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 STA4 0 R/W 3 STA3 0 R/W
H'A0
2 STA2 0 R/W 1 STA1 0 R/W 0
SCI2
STA0 0 R/W
Designates transfer starting address in address space H'FF80 to H'FF9F.
EDAR--End Address Register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 EDA4 0 R/W 3 EDA3 0 R/W
H'A1
2 EDA2 0 R/W 1 EDA1 0 R/W 0
SCI2
EDA0 0 R/W
Designates transfer end address in address space H'FF80 to H'FF9F.
SCR2--Serial Control Register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 I/O 0 R/W 3
H'A2
2 GAP1 0 R/W 1 PS1 0 R/W 0 PS0 0
SCI2
GAP2 0 R/W
R/W
Transmit/Receive Select 0 Receive mode 1 Transmit mode
Gap Insertion 0 0 No gap insertion 0 1 1-clock gap insertion 1 0 2-clock gap insertion 1 1 8-clock gap insertion Transfer Clock Select 0 0 /2, SCK 2 is output pin 0 1 /4, SCK 2 is output pin 1 0 /8, SCK 2 is output pin 1 1 External clock, SCK 2 is input pin Rev. 3.00, 12/94, page 285 of 334
STSR--Status Register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4
SO2 LAST BIT
H'A3
3 OVR
*2
SCI2
2 1 GIT 0 R/W 0 STF 0 R/W
WT 0 R/W*1
0 R/W
R/W*1
Extended Data Bit 0 Pin SO 2 output low 1 Pin SO 2 output high Waiting Flag 0 [Clear condition] When STSR is written 1 [Set condition] When 32-byte data buffer is read or written during transfer Overrun Flag 0 [Clear condition] When STSR is written 1 [Set condition] When overrun occurs Gap Interval Flag 0 Insert gap every 16 bits 1 Insert gap every 8 bits Start/Busy Flag 0 [Read] Transfer stopped [Write] Transfer aborted 1 [Read] Transfer in progress [Write] Start of transfer instructed Notes: 1. Cleared to 0 by a write access to STSR. 2. Not fixed
Rev. 3.00, 12/94, page 286 of 334
SMR1--Serial Mode Register 1
Bit Initial value Read/Write 7 -- 1 -- 6 SMR16 0 W 5 SMR15 0 W 4 SMR14 0 W 3
H'B0
2 SMR12 0 W 1 SMR11 0 W 0
SCI1
SMR13 0 W
SMR10 0 W
Operation Mode Select 00 10 0 0 Clock continuous output mode Clock continuous output mode Not 00 8-bit transfer mode Not 00 16-bit transfer mode
Clock Select 0 0 0 0 /1024, SCK 1 is output pin 1 /256, SCK 1 is output pin 1 0 /64, SCK 1 is output pin 1 /32, SCK 1 is output pin 1 0 0 /16, SCK 1 is output pin 1 /8, SCK 1 is output pin 1 0 /4, SCK 1 is output pin 1 /2, SCK 1 is output pin 1 0 0 0 Not used 1 Not used 1 0 Not used 1 Not used 1 0 0 Not used 1 Not used 1 0 Not used 1 External clock, SCK 1 is input pin
SDRU1--Serial Data Register U1
Bit Initial value Read/Write 7 6 5 4 3
H'B1
2 1 0
SCI1
SDRU17 SDRU16 SDRU15 SDRU14 SDRU13 SDRU12 SDRU11 SDRU10 * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W
Used to set data for transmission and to held received data. 8-bit transfer mode: not used 16-bit transfer mode: upper 8-bits of data register Note: * Not fixed
Rev. 3.00, 12/94, page 287 of 334
SDRL1--Serial Data Register L1
Bit Initial value Read/Write 7 6 5 4 3
H'B2
2 1 0
SCI1
SDRL17 SDRL16 SDRL15 SDRL14 SDRL13 SDRL12 SDRL11 SDRL10 * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W
Used to set data for transmission and to held received data. 8-bit transfer mode: data register 16-bit transfer mode: lower 8-bits of data register Note: * Not fixed
SPR1--Serial Port Register 1
Bit Initial value Read/Write 7
SO1 LAST BIT
H'B3
5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
SCI1
6 -- 1 --
* R/W
Extended Data Bit 0 Pin SO 1 output low 0 Pin SO 1 output high Note: * Not fixed
Rev. 3.00, 12/94, page 288 of 334
VFSR--VFD Segment Control Register
Bit Initial value Read/Write 7 VFLAG 0 R/W 6 KSE 0 R/W 5 -- 1 -- 4 SR4 0 R/W 3 SR3 0 R/W
H'B9
2 SR2 0 R/W
VFD Controller/Driver
1 SR1 0 R/W 0 SR0 0 R/W
Segment Pin Select 00000 Key Scan Enable 0 No key scan interval 1 Key scan interval added 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 VFD/Port Switching Flag 0 All pins doubling as general-purpose ports and VFD pins are used as general-purpose ports. 1 Pins designated as digit or segment pins function as VFD pins. FS0 FS0 to FS1 FS0 to FS2 FS0 to FS3 FS0 to FS4 FS0 to FS5 FS0 to FS6 FS0 to FS7 FS0 to FS8 FS0 to FS9 FS0 to FS10 FS0 to FS11 FS0 to FS12 FS0 to FS13 FS0 to FS14 FS0 to FS15 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 FS0 to FS16 FS0 to FS17 FS0 to FS18 FS0 to FS19 FS0 to FS20 FS0 to FS21 FS0 to FS22 FS0 to FS23 FS0 to FS24 FS0 to FS25 FS0 to FS26 FS0 to FS27 FS0 to FS27 FS0 to FS27 FS0 to FS27 FS0 to FS27
Rev. 3.00, 12/94, page 289 of 334
VFDR--VFD Digit Control Register
Bit Initial value Read/Write 7 FLMO 0 R/W 6 DM2 0 R/W 5 DM1 0 R/W 4 DM0 0 R/W 3 DR3 0 R/W
H'BA
2 DR2 0 R/W
VFD Controller/Driver
1 DR1 0 R/W 0 DR0 0 R/W
Digit Pin Select 0 0 0 0 FD0 to FD15 1 0 0 0 FD0 to FD7 0 0 0 1 FD0 to FD14 1 0 0 1 FD0 to FD6 0 0 1 0 FD0 to FD13 1 0 1 0 FD0 to FD5 0 0 1 1 FD0 to FD12 1 0 1 1 FD0 to FD4 0 1 0 0 FD0 to FD11 1 1 0 0 FD0 to FD3 0 1 0 1 FD0 to FD10 1 1 0 1 FD0 to FD2 0 1 1 0 FD0 to FD9 0 1 1 1 FD0 to FD8 Digit Waveform Select 000 1 10 1 100 1 10 1 Tdigit Tdimmer VFD Mode Bit 0 T digit = 1536/ , T dimmer = 96/ 1 T digit = 768/, Tdimmer = 48/ 1 1 1 0 FD0 to FD1 1 1 1 1 FD0
Rev. 3.00, 12/94, page 290 of 334
DBR--Digit Beginning Register
Bit Initial value Read/Write 7 VFDE 0 R/W 6 DISP 0 R/W 5 -- 1 -- 4 -- 0 R/W 3 DBR3 0 R/W
H'BB
2 DBR2 0 R/W
VFD Controller/Driver
1 DBR1 0 R/W 0 DBR0 0 R/W
Digit/Segment Pin Function Select 0 0 0 0 FD0 to FD7 0 0 0 1 FD1 to FD7, FS7 0 0 1 0 FD2 to FD7, FS7 to FS6 0 0 1 1 FD3 to FD7, FS7 to FS5 0 1 0 0 FD4 to FD7, FS7 to FS4 0 1 0 1 FD5 to FD7, FS7 to FS3 0 1 1 0 FD6 to FD7, FS7 to FS2 0111 1*** Display Bit 0 All segment pins are in non-illuminating state (pull-down state). Digit pins continue operating. Register and RAM values are unchanged. 1 Display RAM contents are output to segment pins. VFD Enable 0 VFD controller/driver is in reset state. 1 VFD controller/driver is in active state. FD7, FS7 to FS1 FS7 to FS0 Note: * Don't care.
Rev. 3.00, 12/94, page 291 of 334
AMR--A/D Mode Register
Bit Initial value Read/Write 7 AMR7 0 R/W Clock Select 0 Conversion period is 64/ 1 Conversion period is 31/ 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 --
H'BC
2 AMR2 0 R/W 1
A/D Converter
0 AMR0 0 R/W
AMR1 0 R/W
Channel Select 0 0 0 Analog input pin is AN0 1 Analog input pin is AN1 1 0 Analog input pin is AN2 1 Analog input pin is AN3 1 0 0 Analog input pin is AN4 1 Analog input pin is AN5 1 0 Analog input pin is AN6 1 Analog input pin is AN7
ADRR--A/D Result Register
Bit Initial value Read/Write 7 ADR7 * R 6 ADR6 * R 5 ADR5 * R 4 ADR4 * R 3 ADR3 * R
H'BD
2 ADR2 * R 1
A/D Converter
0 ADR0 * R
ADR1 * R
A/D Conversion Result Note: * Not fixed
Rev. 3.00, 12/94, page 292 of 334
ADSR--A/D Start Register
Bit Initial value Read/Write 7 ADSF 0 R/W A/D Start Flag 0 [Read] A/D conversion stopped or complete [Write] A/D conversion aborted 1 [Read] A/D conversion in progress [Write] A/D conversion start instruction 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 --
H'BE
2 -- 1 -- 1 -- 1 --
A/D Converter
0 -- 1 --
TMA--Timer Mode Register A
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3
H'C0
2 TMA2 0 R/W 1 TMA1 0 R/W
Timer A
0 TMA0 0 R/W
TMA3 0 R/W
Clock Select 0 0 0 0 Input source PSS, /8192 1 Input source PSS, /4096 1 0 Input source PSS, /2048 1 Input source PSS, /512 1 0 0 Input source PSS, /256 1 Input source PSS, /128 1 0 Input source PSS, /32 1 Input source PSS, /8 1 0 0 0 Input source PSW, 2 s 1 Input source PSW, 1 s 1 0 Input source PSW, 0.5 s 1 Input source PSW, 125 ms 1 0 0 PSW and TCA reset 1 10 1
Rev. 3.00, 12/94, page 293 of 334
TCA--Timer Counter A
Bit Initial value Read/Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R
H'C1
2 TCA2 0 R 1 TCA1 0 R
Timer A
0 TCA0 0 R
Count Value
TMB--Timer Mode Register B
Bit Initial value Read/Write 7 TMB7 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 --
H'C2
2 TMB2 0 R/W 1 TMB1 0 R/W
Timer B
0 TMB0 0 R/W
Clock Select 0 0 0 Internal clock, /8192 1 Internal clock, /2048 1 0 Internal clock, /512 1 Internal clock, /256 1 0 0 Internal clock, /128 1 Internal clock, /32 1 0 Internal clock, /8 1 External clock, choice of rising or falling edge Auto Reload Function Select 0 Internal timer 1 Auto-reload timer
Rev. 3.00, 12/94, page 294 of 334
TCB--Timer Counter B
Bit Initial value Read/Write 7 TCB7 0 R 6 TCB6 0 R 5 TCB5 0 R 4 TCB4 0 R 3 TCB3 0 R
H'C3
2 TCB2 0 R 1 TCB1 0 R
Timer B
0 TCB0 0 R
Count Value
TLB--Timer Load Register B
Bit Initial value Read/Write 7 TLB7 0 W 6 TLB6 0 W 5 TLB5 0 W 4 TLB4 0 W 3 TLB3 0 W
H'C3
2 TLB2 0 W 1 TLB1 0 W
Timer B
0 TLB0 0 W
Load Value Setting
Rev. 3.00, 12/94, page 295 of 334
TMC--Timer Mode Register C
Bit Initial value Read/Write 7 TMC7 0 R/W 6 TMC6 0 R/W 5 TMC5 0 R/W 4 -- 1 -- 3 -- 1 --
H'C4
2 TMC2 0 R/W 1 TMC1 0 R/W
Timer C
0 TMC0 0 R/W
Clock Select 0 0 0 Internal clock, /8192 1 Internal clock, /2048 1 0 Internal clock, /512 1 Internal clock, /256 1 0 0 Internal clock, /128 1 Internal clock, /32 1 0 Internal clock, /8 1 External clock, choice of rising or falling edge Count-Up/Down Control 0 0 Up-counter 1 Down-counter 1 * Hardware control via pin P9 7/UD. High is down, low is up. Note: * Don't care. Auto-Reload Function Select 0 Internal timer 1 Auto-reload timer
TCC--Timer Counter C
Bit Initial value Read/Write 7 TCC7 0 R 6 TCC6 0 R 5 TCC5 0 R 4 TCC4 0 R 3 TCC3 0 R
H'C5
2 TCC2 0 R 1 TCC1 0 R
Timer C
0 TCC0 0 R
Count Value
Rev. 3.00, 12/94, page 296 of 334
TLC--Timer Load Register C
Bit Initial value Read/Write 7 TLC7 0 W 6 TLC6 0 W 5 TLC5 0 W 4 TLC4 0 W 3 TLC3 0 W
H'C5
2 TLC2 0 W 1 TLC1 0 W
Timer C
0 TLC0 0 W
Reload Value Setting
TMD--Timer Mode Register D
Bit Initial value Read/Write 7 CLR 0 W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 --
H'C6
2 -- 1 -- 1 -- 1 --
Timer D
0 EDG 0 R/W
Edge Select 0 Count up at falling edge of EVENT pin input 1 Count up at rising edge of EVENT pin input Counter Clear 0 After this bit is set to 1 and TCD is initialized, it is automatically cleared by hardware. 1 TCD is initialized to H'00.
TCD--Timer Counter D
Bit Initial value Read/Write 7 TCD7 0 R 6 TCD6 0 R 5 TCD5 0 R 4 TCD4 0 R 3 TCD3 0 R
H'C7
2 TCD2 0 R 1 TCD1 0 R
Timer D
0 TCD0 0 R
Count Value
Rev. 3.00, 12/94, page 297 of 334
TME--Timer Mode Register E
Bit Initial value Read/Write 7 TME7 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 --
H'C8
2 TME2 0 R/W 1 TME1 0 R/W
Timer E
0 TME0 0 R/W
Auto-Reload Function Select 0 Internal timer 1 Auto-reload timer
Clock Select 0 0 0 Internal clock, /8192 1 Internal clock, /4096 1 0 Internal clock, /2048 1 Internal clock, /512 1 0 0 Internal clock, /256 1 Internal clock, /128 1 0 Internal clock, /32 1 Internal clock, /8
TCE--Timer Counter E
Bit Initial value Read/Write 7 TCE7 0 R 6 TCE6 0 R 5 TCE5 0 R 4 TCE4 0 R 3 TCE3 0 R
H'C9
2 TCE2 0 R 1 TCE1 0 R
Timer E
0 TCE0 0 R
Count Value
TLE--Timer Load Register E
Bit Initial value Read/Write 7 TLE7 0 W 6 TLE6 0 W 5 TLE5 0 W 4 TLE4 0 W 3 TLE3 0 W
H'C9
2 TLE2 0 W 1 TLE1 0 W
Timer E
0 TLE0 0 W
Reload Value Setting
Rev. 3.00, 12/94, page 298 of 334
PWCR--PWM Control Register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- Clock Select 3 -- 1 --
H'CC
2 -- 1 -- 1 -- 1 --
14-bit PWM
0 PWCR0 0 W
0 The input clock is /2. The conversion period is 16384/ , with a minimum modulation width of 1/ . 1 The input clock is /4. The conversion period is 32768/ , with a minimum modulation width of 2/ .
PWDRU--PWM Data Register U
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 0 W 4 0 W 3 0 W
H'CD
2 0 W 1 0 W
14-bit PWM
0 0 W
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0
Upper 6 Bits of Data for PWM Waveform Generation
PWDRL--PWM Data Register L
Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W
H'CE
2 0 W 1 0 W
14-bit PWM
0 0 W
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
Lower 8 Bits of Data for PWM Waveform Generation
Rev. 3.00, 12/94, page 299 of 334
PDR0--Port Data Register 0
Bit Initial value Read/Write 7 PDR0 7 -- R 6 PDR0 6 -- R 5 PDR0 5 -- R 4 PDR0 4 -- R 3
H'D0
2 PDR0 2 -- R 1 PDR0 1 -- R
I/O Ports
0 PDR0 0 -- R
PDR03 -- R
PDR1--Port Data Register 1
Bit Initial value Read/Write 7 -- --* -- 6 -- --* -- 5 PDR1 5 0 R/W 4 PDR14 0 R/W 3
H'D1
2 PDR1 2 0 R/W 1 PDR11 0 R/W
I/O Ports
0 PDR10 0 R/W
PDR13 0 R/W
Note: * Pins P16 and P17 are input-only pins; whenever they are read, the pin level is read out.
PDR3--Port Data Register 3
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3
H'D3
2 PDR3 2 0 R/W 1 PDR3 1 0 R/W
I/O Ports
0 PDR3 0 0 R/W
PDR3 3 0 R/W
PDR4--Port Data Register 4
Bit Initial value Read/Write 7 PDR4 7 0 R/W 6 PDR4 6 0 R/W 5 PDR4 5 0 R/W 4 PDR44 0 R/W 3
H'D4
2 PDR4 2 0 R/W 1 PDR4 1 0 R/W
I/O Ports
0 PDR4 0 0 R/W
PDR4 3 0 R/W
PDR5--Port Data Register 5
Bit Initial value Read/Write 7 PDR5 7 0 R/W 6 PDR5 6 0 R/W 5 PDR5 5 0 R/W 4 PDR54 0 R/W 3
H'D5
2 PDR5 2 0 R/W 1 PDR5 1 0 R/W
I/O Ports
0 PDR5 0 0 R/W
PDR5 3 0 R/W
Rev. 3.00, 12/94, page 300 of 334
PDR6--Port Data Register 6
Bit Initial value Read/Write 7 PDR6 7 0 R/W 6 PDR6 6 0 R/W 5 PDR6 5 0 R/W 4 PDR64 0 R/W 3
H'D6
2 PDR6 2 0 R/W 1 PDR6 1 0 R/W
I/O Ports
0 PDR6 0 0 R/W
PDR6 3 0 R/W
PDR7--Port Data Register 7
Bit Initial value Read/Write 7 PDR7 7 0 R/W 6 PDR7 6 0 R/W 5 PDR7 5 0 R/W 4 PDR74 0 R/W 3
H'D7
2 PDR7 2 0 R/W 1 PDR7 1 0 R/W
I/O Ports
0 PDR7 0 0 R/W
PDR7 3 0 R/W
PDR8--Port Data Register 8
Bit Initial value Read/Write 7 PDR8 7 0 R/W 6 PDR8 6 0 R/W 5 PDR8 5 0 R/W 4 PDR84 0 R/W 3
H'D8
2 PDR8 2 0 R/W 1 PDR8 1 0 R/W
I/O Ports
0 PDR8 0 0 R/W
PDR8 3 0 R/W
PDR9--Port Data Register 9
Bit Initial value Read/Write 7 PDR9 7 0 R/W 6 PDR9 6 0 R/W 5 PDR9 5 0 R/W 4 PDR94 0 R/W 3
H'D9
2 PDR9 2 0 R/W 1 PDR9 1 0 R/W
I/O Ports
0 PDR9 0 0 R/W
PDR9 3 0 R/W
PDRA--Port Data Register A
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 --
H'DA
2 -- 1 -- 1 PDRA 1 0 R/W
I/O Ports
0 PDRA 0 0 R/W
Rev. 3.00, 12/94, page 301 of 334
PCR1--Port Control Register 1
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 PCR15 0 W 4 PCR14 0 W 3
H'E1
2 PCR12 0 W 1 PCR11 0 W
I/O Ports
0 PCR10 0 W
PCR13 0 W
Port 1 I/O Select 0 Input port 1 Output port
PCR8--Port Control Register 8
Bit Initial value Read/Write 7 PCR8 7 0 W 6 PCR8 6 0 W 5 PCR85 0 W 4 PCR84 0 W 3
H'E8
2 PCR82 0 W 1 PCR81 0 W
I/O Ports
0 PCR80 0 W
PCR83 0 W
Port 8 I/O Select 0 Input port 1 Output port
PCR9--Port Control Register 9
Bit Initial value Read/Write 7 PCR9 7 0 W 6 PCR9 6 0 W 5 PCR95 0 W 4 PCR94 0 W 3 PCR93 0 W
H'E9
2 PCR92 0 W 1 PCR91 0 W
I/O Ports
0 PCR90 0 W
Port 9 I/O Select 0 Input port 1 Output port
Rev. 3.00, 12/94, page 302 of 334
PCRA--Port Control Register A
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 --
H'EA
2 -- 1 -- 1 PCRA 1 0 W
I/O Ports
0 PCRA 0 0 W
Port A I/O Select 0 Input port 1 Output port
Rev. 3.00, 12/94, page 303 of 334
PMR1--Port Mode Register 1
Bit Initial value Read/Write 7
NOISE CANCEL
H'EB
5 IRQC5 0 R/W 4 IRQC4 0 R/W 3 IRQC3 0 R/W 2 IRQC2 0 R/W 1 IRQC1 0 R/W
I/O Ports
0 IRQC0 0 R/W
6 EVENT 0 R/W
0 R/W
P16/EVENT Pin Function Switch 0 P16 pin function 1 EVENT pin function Noise Cancel 0 IRQ0 pin noise cancel function off 1 IRQ0 pin noise cancel function on
P10/IRQ0 Pin Function Switch 0 P10 pin function 1 IRQ0 pin function P11/IRQ1 Pin Function Switch 0 P11 pin function 1 IRQ1 pin function P12/IRQ2 Pin Function Switch 0 P12 pin function 1 IRQ2 pin function P13/IRQ3 Pin Function Switch 0 P13 pin function 1 IRQ3 pin function P14/IRQ4 Pin Function Switch 0 P14 pin function 1 IRQ4 pin function
P15/IRQ5 /TMOE Pin Function Switch 0 P15/TMOE pin function* 1 IRQ5 pin function Note: * On switching between P15 and TMOE pin functions see under PMR4.
Rev. 3.00, 12/94, page 304 of 334
PMR2--Port Mode Register 2
Bit Initial value Read/Write 7
UP/ DOWN
H'EC
5 SI2 0 R/W 4 SCK2 0 R/W 3 SO1 0 R/W 2 SI1 0 R/W 1 SCK1 0 R/W
I/O Ports
0 PWM 0 R/W
6 SO2 0 R/W
0 R/W
P96 /SO2 Pin Function Switch 0 P9 6 pin function 1 SO2 pin function P97 /UD Pin Function Switch 0 P97 pin function 1 UD pin function
P9 0/PWM Pin Function Switch 0 P9 0 pin function 1 PWM pin function P9 1/SCK1 Pin Function Switch 0 P91 pin function 1 SCK 1 pin function P92 /SI 1 pin function switch 0 P92 pin function 1 SI1 pin function P9 3 /SO 1Pin Function Switch 0 P93 pin function 1 SO1 pin function P9 4/SCK2 Pin Function Switch 0 P94 pin function 1 SCK2 pin function P9 5/SI 1/CS Pin Function Switch 0 P95 pin function 1 SI 1/CS pin function*
Note: * On switching between SI1 and CS pin functions see under PMR3.
Rev. 3.00, 12/94, page 305 of 334
PMR3--Port Mode Register 3
Bit Initial value Read/Write 7 -- 1 -- 6
SO2 PMOS
H'ED
5 CS 0 R/W 4 -- 1 -- 3
SO1 PMOS
I/O Ports
2 1 -- 1 -- 0 -- 1 --
-- 1 --
0 R/W
0 R/W
SO1 Pin PMOS On/Off 0 SO1 pin PMOS buffer on. CMOS output. 1 SO1 pin PMOS off. NMOS open drain output. Chip Select Output Select PMR2 PMR3 SI2 CS P9 5/SI 2/CS pin function switch 0 1 0 1 0 1 SO2 Pin PMOS On/Off 0 SO2 pin PMOS buffer on. CMOS output. 1 SO2 pin PMOS off. NMOS open drain output. SI 2 pin function CS pin function P95 pin function
Rev. 3.00, 12/94, page 306 of 334
PMR4--Port Mode Register 4
Bit Initial value Read/Write 7 TEO 0 R/W 6 TEO ON 0 R/W 5 FREQ 0 R/W 4 VRFR 0 R/W 3 -- 1 --
H'EE
2 -- 1 -- 1 -- 1 --
I/O Ports
0 -- 1 --
Timer E Output Control PMR1 IRQC5 0 0 0 0 0 P15 /IRQ 5/TMOE Pin TEO TEO ON FREQ VRFR Function Switch 0 1 1 1 1 * 0 1 1 1 * * 0 1 * * * 0 0 1 P15 pin function PMR4 Pin Status Standard I/O port
TMOE pin function (off) Low-level output TMOE pin function (on) Fixed-frequency output: /2048 TMOE pin function (on) Fixed-frequency output: /1024 TMOE pin function (on) Random frequency output: toggle output with each Timer E overflow IRQ5 pin function External interrupt input
1
*
*
*
*
Note: * Don't care.
PMR0--Port Mode Register 0
Bit Initial value Read/Write 7 AN7 0 W 6 AN6 0 W 5 AN5 0 W 4 AN4 0 W 3 AN3 0 W
H'EF
2 AN2 0 W 1 AN1 0 W
I/O Ports
0 AN0 0 W
Analog Input Select 0 General-purpose input port 1 Analog input channel
Rev. 3.00, 12/94, page 307 of 334
SYSCR1--System Control Register 1
Bit Initial value Read/Write 7 SSBY 0 R/W
*1
H'F0
4 STS0 0 R/W 3 LSON 0 R/W 2 -- 0 R/W
*2
System Control
1 -- 0 -- 0 -- 0 --
6 STS2 0 R/W
5 STS1 0 R/W
Low-Speed on Flag
Standby Timer Select
0 CPU runs on system clock ( ) 1 CPU runs on subclock ( SUB)
0 0 0 Wait time = 8192 states 0 0 1 Wait time = 16384 states 0 1 0 Wait time = 32768 states 0 1 1 Wait time = 65536 states 1
*3 *3
Wait time = 131072 states
Standby 0 Sleep mode entered after SLEEP instruction is executed. 1 Standby mode entered after SLEEP instruction is executed. Notes: 1. Write is enabled in active mode only. 2. This relates to the transitions between operation modes, so functioning depends on the combination of this bit with other control bits and interrupts. For details see 3.3, System Modes. 3. Don't care.
SYSCR2--System Control Register 2
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 DTON 0 W*
H'F1
2 -- 1 -- 1 -- 0
System Control
0 -- 0 R/W
R/W
Direct Transfer on Flag 0 In subactive mode, watch mode is entered when a SLEEP instruction is executed. 1 In subactive mode, when LSON bit = 0, active mode is entered via watch mode when a SLEEP instruction is executed. Note: * Write is enabled in subactive mode only. Rev. 3.00, 12/94, page 308 of 334
IEGR--IRQ Edge Select Register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 IEG4 0 R/W 3 -- 1 --
H'F2
2 -- 1 -- 1
System Control
0 IEG0 0 R/W
IEG1 0 R/W
IRQ 4 Input Edge Select 0 Rising edge detected. 1 Falling edge detected.
IRQ 0 Input Edge Select 0 Rising edge detected. 1 Falling edge detected.
IRQ 1 Input Edge Select 0 Rising edge detected. 1 Falling edge detected.
IENR1--Interrupt Enable Register 1
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 IEN5 0 R/W 4 IEN4 0 R/W 3 IEN3 0 R/W
H'F3
2 IEN2 0 R/W 1
System Control
0 IEN0 0 R/W
IEN1 0 R/W
IRQ 5 Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled. IRQ 4 Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled.
IRQ 0 Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled. IRQ 1 Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled.
IRQ 3 Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled.
IRQ 2 Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled.
Rev. 3.00, 12/94, page 309 of 334
IENR2--Interrupt Enable Register 2
Bit Initial value Read/Write 7 -- 0 R/W 6 -- 0 R/W 5 IENDT 0 R/W 4 IENTE 0 R/W 3
H'F4
2 IENTC 0 R/W 1
System Control
0 IENTA 0 R/W
IENTD 0 R/W
IENTB 0 R/W
DTON Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled. Timer E Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled.
Timer A Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled. Timer B Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled.
Timer D Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled.
Timer C Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled.
IENR3--Interrupt Enable Register 3
Bit Initial value Read/Write 7 IENAD 0 R/W 6 IENKS 0 R/W 5 -- 1 -- 4 -- 1 -- 3 -- 1 --
H'F5
2 -- 1 -- 1
System Control
0 IENS1 0 R/W
IENS2 0 R/W
Key Scan Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled. A/D Conversion Complete Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled. SCI2 Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled. SCI1 Interrupt Enable 0 Interrupts disabled. 1 Interrupts enabled.
Rev. 3.00, 12/94, page 310 of 334
IRR1--Interrupt Request Register 1
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 IRRI5 0 R/W* 4 IRRI4 0 R/W* 3 IRRI3 0 R/W*
H'F6
2 IRRI2 0 R/W* 1
System Control
0 IRRI0 0 R/W*
IRRI1 0 R/W*
IRQ 5 Interrupt Request 0 No interrupt request 1 Interrupt request raised IRQ 4 Interrupt Request 0 No interrupt request 1 Interrupt request raised
IRQ 0 Interrupt Request 0 No interrupt request 1 Interrupt request raised IRQ 1 Interrupt Request 0 No interrupt request 1 Interrupt request raised
IRQ 3 Interrupt Request 0 No interrupt request 1 Interrupt request raised Note: * Write is enabled only for clearing flag to 0.
IRQ 2 Interrupt Request 0 No interrupt request 1 Interrupt request raised
Rev. 3.00, 12/94, page 311 of 334
IRR2--Interrupt Request Register 2
Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 IRRDT 0 R/W* 4 IRRTE 0 R/W* 3
H'F7
2 IRRTC 0 R/W* 1
System Control
0 IRRTA 0 R/W*
IRRTD 0 R/W*
IRRTB 0 R/W*
DTON Interrupt Request 0 No interrupt request 1 Interrupt request raised Timer E Interrupt Request 0 No interrupt request 1 Interrupt request raised
Timer A Interrupt Request 0 No interrupt request 1 Interrupt request raised Timer B Interrupt Request 0 No interrupt request 1 Interrupt request raised
Timer D Interrupt Request 0 No interrupt request 1 Interrupt request raised Note: * Write is enabled only for clearing flag to 0.
Timer C Interrupt Request 0 No interrupt request 1 Interrupt request raised
IRR3--Interrupt Request Register 3
Bit Initial value Read/Write 7 IRRAD 0 R/W* 6 IRRKS 0 R/W* 5 -- 1 -- 4 -- 1 -- 3 -- 1 --
H'F8
2 -- 1 -- 1
System Control
0 IRRS1 0 R/W*
IRRS2 0 R/W*
Key Scan Interrupt Request 0 No interrupt request 1 Interrupt request raised A/D Conversion Complete Interrupt Request 0 No interrupt request 1 Interrupt request raised Note: * Write is enabled only for clearing flag to 0. Rev. 3.00, 12/94, page 312 of 334 SCI2 Interrupt Request 0 No interrupt request 1 Interrupt request raised SCI1 Interrupt Request 0 No interrupt request 1 Interrupt request raised
Appendix C I/O Port Block Diagrams
C.1 Port 0 Block Diagram
PMR0 (bit n) P0n
Internal data bus A/D converter VIN SEL
PMR0: Port mode register 0 n = 0 to 7
Figure C-1 Port 0 Block Diagram
Rev. 3.00, 12/94, page 313 of 334
C.2 Port 1 Block Diagram
STBY
VCC Option
VCC
PDR1 (bit n) P1n PMR1 (bit n) PCR1 (bit n) VSS
Internal data bus
IRQ PDR1: Port data register 1 PMR1: Port mode register 1 PCR1: Port control register 1 n = 0 to 4 P1 0 : P1 1 : P1 2 : P1 3 : P1 4 : IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4
Figure C-2 (a) Port 1 Block Diagram (pins P10 to P14)
Rev. 3.00, 12/94, page 314 of 334
STBY Timer E TMOE TEO PDR1 (bit 5) P15 PMR1 (bit 5) PCR1 (bit 5) VSS
VCC Option
VCC
Internal data bus
IRQ5 PDR1: Port data register 1 PMR1: Port mode register 1 PCR1: Port control register 1 TEO: Port mode register 4, bit 7 TMOE: Square wave output
Figure C-2 (b) Port 1 Block Diagram (pin P15)
Rev. 3.00, 12/94, page 315 of 334
STBY
Option PDR1 (bit 6) P16 Internal data bus Timer D EVENT EDG (edge select) PMR1: Port mode register 1
Figure C-2 (c) Port 1 Block Diagram (pin P16)
Option P17 VSS Vdisp
Internal data bus
Figure C-2 (d) Port 1 Block Diagram (pin P17)
Rev. 3.00, 12/94, page 316 of 334
C.3 Port 3 Block Diagram
STBY Decoder VCC
VFD controller/ driver SR 4 to SR 0 VFLAG LTCLK RAM SGDL DATA
P3 n PDR3 (bit n) Option Internal data bus
Vdisp
PDR3: Port data register 3 n = 0 to 3 SGDL: Segment data latch LTCLK: Segment data latch clock SR 4 to SR 0 : VFD segment control register bits 4 to 0 VFLAG: VFD segment control register bit 7
Figure C-3 Port 3 Block Diagram
Rev. 3.00, 12/94, page 317 of 334
C.4 Port 4 Block Diagram
STBY Decoder VCC
VFD controller/ driver SR 4 to SR 0 VFLAG LTCLK RAM SGDL DATA
P4 n PDR4 (bit n) Option Internal data bus
Vdisp
PDR4: Port data register 4 n = 0 to 7 SGDL: Segment data latch LTCLK: Segment data latch clock SR 4 to SR 0 : VFD segment control register bits 4 to 0 VFLAG: VFD segment control register bit 7
Figure C-4 Port 4 Block Diagram
Rev. 3.00, 12/94, page 318 of 334
C.5 Port 5 Block Diagram
STBY Decoder VCC
VFD controller/ driver SR 4 to SR 0 VFLAG LTCLK RAM SGDL DATA
P5 n PDR5 (bit n) Option Internal data bus
Vdisp
PDR5: Port data register 5 n = 0 to 7 SGDL: Segment data latch LTCLK: Segment data latch clock SR 4 to SR 0 : VFD segment control register bits 4 to 0 VFLAG: VFD segment control register bit 7
Figure C-5 Port 5 Block Diagram
Rev. 3.00, 12/94, page 319 of 334
C.6 Port 6 Block Diagram
VFD controller/ driver FD STBY DBR 3 to DBR 0 VCC Decoder DR 3 to DR 0 SR 4 to SR 0 VFLAG LTCLK RAM P6 n SGDL DATA
Option
PDR6 (bit n) Internal data bus
Vdisp
PDR6: Port data register 6 n = 0 to 7 SGDL: Segment data latch LTCLK: Segment data latch clock FD: Digit output waveform DBR 3 to DBR 0 : Digit beginning register bits 3 to 0 DR 3 to DR 0 : VFD digit control register bits 3 to 0 SR 4 to SR 0 : VFD segment control register bits 4 to 0 VFLAG: VFD segment control register bit 7
Figure C-6 Port 6 Block Diagram
Rev. 3.00, 12/94, page 320 of 334
C.7 Port 7 Block Diagram
VFD controller/ driver STBY FD Decoder DR 3 to DR 0 VFLAG
VCC
P7 n
PDR7 (bit n)
Internal data bus
Option
Vdisp
PDR7: Port data register 7 n = 0 to 7 FD: Digit output waveform DR 3 to DR 0 : VFD digit control register bits 3 to 0 VFLAG: VFD segment control register bit 7
Figure C-7 Port 7 Block Diagram
Rev. 3.00, 12/94, page 321 of 334
C.8 Port 8 Block Diagram
STBY
VCC
VCC
PDR8 (bit n) P8n PCR8 (bit n) Internal data bus
GND
PDR8: Port data register 8 PCR8: Port control register 8 n = 0 to 7
Figure C-8 Port 8 Block Diagram (pins P80 and P81)
Rev. 3.00, 12/94, page 322 of 334
C.9 Port 9 Block Diagram
STBY
VCC Option
VCC
PWM PWM PDR9 (bit 0)
P90
PMR2 (bit 0) PCR9 (bit 0) VSS
Internal data bus
PDR9: Port data register 9 PMR2: Port mode register 2 PCR9: Port control register 9
Figure C-9 (a) Port 9 Block Diagram (pin P90)
Rev. 3.00, 12/94, page 323 of 334
STBY SCI VCC Option PDR9 (bit n) P9n PMR2 (bit n) PCR9 (bit n) VSS VCC EXCK SCKO SCKi
Internal data bus
PDR9: Port data register 9 PMR2: Port mode register 2 PCR9: Port control register 9 n = 1 and 4
Figure C-9 (b) Port 9 Block Diagram (pins P91 and P94)
Rev. 3.00, 12/94, page 324 of 334
STBY
VCC Option
VCC
PDR9 (bit 2) P92 PMR2 (bit 2) PCR9 (bit 2) VSS SCI SI PDR9: Port data register 9 PMR2: Port mode register 2 PCR9: Port control register 9
Internal data bus
Figure C-9 (c) Port 9 Block Diagram (pin P92)
Rev. 3.00, 12/94, page 325 of 334
STBY
PMR3 P93 : bit 3 P96 : bit 6 SCI SO PDR9 (bit n)
VCC Option
VCC
P9n
PMR2 (bit n) PCR9 (bit n) VSS
Internal data bus
PDR9: Port data register 9 PMR2: Port mode register 2 PCR9: Port control register 9 n = 3 and 6
Figure C-9 (d) Port 9 Block Diagram (pins P93 and P96)
Rev. 3.00, 12/94, page 326 of 334
STBY PMR3 (bit 5)
VCC Option
VCC
SCI CS SI
PDR9 (bit 5) P95 PMR2 (bit 5) PCR9 (bit 5) VSS
Internal data bus
PDR9: Port data register 9 PMR2: Port mode register 2 PCR9: Port control register 9
Figure C-9 (e) Port 9 Block Diagram (pin P95)
Rev. 3.00, 12/94, page 327 of 334
STBY
VCC Option
VCC
PDR9 (bit 7) P97 PMR2 (bit 7) PCR9 (bit 7) VSS Timer C UD PDR9: Port data register 9 PMR2: Port mode register 2 PCR9: Port control register 9
Internal data bus
Figure C-9 (f) Port 9 Block Diagram (pin P97)
Rev. 3.00, 12/94, page 328 of 334
C.10 Port A Block Diagram
STBY
VCC Option
VCC
PDRA (bit n) PAn PCRA (bit n) Internal data bus
VSS
PDRA: Port data register A PCRA: Port control register A n = 0 and 1
Figure C-10 Port A Block Diagram
Rev. 3.00, 12/94, page 329 of 334
Appendix D Port States in Each Processing State
Table D-1 Port States
Mode Port Pins P07 to P00 P17 P16 P15 to P10 P33 to P30 P47 to P40 P57 to P50 P67 to P60 P77 to P70 P87 to P80 P97 to P90 PA1, PA0 Reset Hi-z Hi-z Hi-z or pull-up Hi-z or pull-up Hi-z or pull-down Hi-z or pull-down Hi-z or pull-down Hi-z or pull-down Hi-z or pull-down Hi-z or pull-up Hi-z or pull-up Hi-z or pull-up Sleep Hi-z Hi-z Hi-z or pull-up prev. state prev. state prev. state prev. state prev. state prev. state prev. state prev. state prev. state Standby Hi-z Hi-z Hi-z Hi-z Hi-z or pull-down Hi-z or pull-down Hi-z or pull-down Hi-z or pull-down Hi-z or pull-down Hi-z Hi-z Hi-z Watch Hi-z Hi-z Hi-z Hi-z Hi-z or pull-down Hi-z or pull-down Hi-z or pull-down Hi-z or pull-down Hi-z or pull-down Hi-z Hi-z Hi-z Subactive Hi-z Hi-z Hi-z Hi-z Hi-z or pull-down Hi-z or pull-down Hi-z or pull-down Hi-z or pull-down Hi-z or pull-down Hi-z Hi-z Hi-z Active Standard input port High-voltage input port Standard input port Standard I/O port High-voltage I/O port High-voltage I/O port High-voltage I/O port High-voltage I/O port High-voltage I/O port Standard I/O port Standard I/O port Standard I/O port
Notation: Hi-z: High-impedance state Prev. state: Input pins are in high-impedance state. Output pins hold their previous output. Hi-z or pull-up: Standard ports for which the pull-up MOS mask option is chosen are in pull-up state; ports without the pull-up MOS option are in high-impedance state. Hi-z or pull-down: High-voltage ports for which the pull-down resistor mask option is chosen are in pull-down state; ports without the pull-down resistor option are in highimpedance state.
Rev. 3.00, 12/94, page 330 of 334
Notes: 1. When pull-up MOS is chosen as a mask option with standard ports, the pull-ups are always on in active mode and sleep mode, regardless of the port control register (PCR) and port data register (PDR) settings. The pull-ups are off in power-down modes other than sleep mode. 2. The input gates of pins selected for peripheral function input remain on even in powerdown modes. This means the input levels must be fixed in order to avoid increased power dissipation. 3. The states indicated above for P17 are when this pin is designated as a high-voltage input pin by mask option.
Rev. 3.00, 12/94, page 331 of 334
Appendix E List of Mask Options
HD6433723, HD6433724, HD6433725, HD6433726, HD6433753, and HD6433754
Please indicate the selected specifications by marking the appropriate box (with an x or mark). The shaded boxes cannot be selected.
Date of order Company Address Name ROM code name LSI model no. , 19
(1) I/O Options
B: With MOS pull-up D: No resistor pull-down
Pin P10/IRQ0 P11/IRQ1 P12/IRQ2 P13/IRQ3 P14/IRQ4 P15/IRQ5/TMOE P16/EVENT P30/FS24 P31/FS25 P32/FS26 P33/FS27 P40/FS16 P41/FS17 P42/FS18 P43/FS19 P44/FS20 P45/FS21 P46/FS22 P47/FS23 P17/Vdisp I/O Standard pins
C: No MOS pull-up E: With resistor pull-down
Pin P50/FS15 P51/FS14 P52/FS13 P53/FS12 P54/FS11 P55/FS10 P56/FS9 P57/FS8 P60/FD0/FS7 P61/FD1/FS6 P62/FD2/FS5 P63/FD3/FS4 P64/FD4/FS3 P65/FD5/FS2 P66/FD6/FS1 P67/FD7/FS0 P70/FD8 P71/FD9 P72/FD10 P73/FD11 P74/FD12 P75/FD13 P76/FD14 P77/FD15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O option BCDE
HD6433723 HD6433725 HD6433753
HD6433724 HD6433726 HD6433754
I/O option BCDE
I/O option BCDE
Pin P80 P81 P82 P83 P84 P85 P86 P87 P90/PWM P91/SCK1 P92/SI1 P93/SO1 P94/SCK2 P95/SI2/CS P96/SO2 P97/UD PA0 PA1
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I Fill in (2) below
(2) P17/Vdisp
P17: No MOS pull-down (D) Vdisp Note: If E (resistor pull-down) is selected as an option for one or more high-voltage pins, Vdisp must be selected for the P17/Vdisp pin.
High-voltage pins
High-voltage pins
(4) Oscillator at OSC 1 and OSC2
Crystal oscillator Ceramic oscillator External clock fOSC = fOSC = fOSC = MHz MHz MHz
(3) Package
FP-80A FP-80B
(5) Oscillator at X 1 and X2
Used Not used fx = 32.768 kHz X1 = VCC
Notes: 1. The wide temperature range specification and I specification are special specifications. There is no J specification for these products. Please contact your local Hitachi representative for details. 2. ROM data submitted in an EPROM must be written starting from address H'0000, in accord with the memory map of the particular LSI. For data outside the ROM area on the memory map use H'FF.
Rev. 3.00, 12/94, page 332 of 334
Standard pins
Appendix F Rise Time/Fall Time of High-Voltage Pins
With the mask ROM versions there is a choice of high-voltage pin output waveforms. Either PMOS open drain (D) or pull-down MOS (E) may be selected. (Only PMOS open drain is available as the output waveform of high-voltage pins on ZTATTM versions.) The rise time tr and fall time tf of high-voltage pin output can be estimated as follows. It is possible to gauge tr and tf based on the time derived from time constant = C.R (time up to 63% of rise or fall). tr: The time constant is determined by the PMOS "on" resistance and load capacitance. The DC characteristic for PMOS "on" resistance is approximately 200 (based on the equation VOH = VCC - 3 V at -IOH = 15 mA, 3/15 x 10-3 = 200). The AC characteristic, however, includes the non-saturation state when the PMOS is on (it is not a steady-state power source), resulting in a longer time constant. Assuming a load capacitance of 30 pF at high-voltage pins, a minimum value of approximately 20 ns is derived. tf: The time constant is determined by pull-down resistance and load capacitance (including wiring capacitance, etc.). As a ZTAT version example, assuming an external pull-down resistance of 5 k and load capacitance of 30 pF, the following is derived. tf 5 x 103 x 30 x 10-12 = 150 x 10-9 (150 ns) Resistance of an optional pull-down resistor built-in the mask ROM version varies from 45 k to 300 k, so all due care must be taken in timing design.
VCC 63% 63%
Pull-down resistance Load capacitance
tr
tf
H8/3724
VSS
Note: If pull-down resistance is made too small in an attempt to speed up the fall time, -IOH will increase, limiting the output high-level voltage (VOH). Pull-down resistance must be set to a suitable value taking into consideration both operation speed and the output high level.
Rev. 3.00, 12/94, page 333 of 334
Appendix G External Dimensions
Figures G-1 and G-2 show the external dimensions of the FP-80A and FP-80B packages, respectively, for H8/3724 and H8/3754 Series.
Unit: mm
0.65 mm Pitch 60 61 17.2 0.3 17.2 0.3
14.0
41 40 0.65
80 1
0.30 0.10
21 20
+0.20 -0.16
0.12 M
3.05 Max
2.70
+0.08 -0.05
1.60
0.17
0 - 5
0.10
0.10
0.80 0.30
Figure G-1 External Dimensions (FP-80A)
Unit: mm
0.8 mm Pitch 24.8 0.4
20.0
64 65 18.8 0.4
14.0
41 40
80 1 0.35 0.10 24
0.15 M
25 3.10 Max
+0.20 -0.16
0.8
0.17 0.05
2.70
2.40
0 - 10
0.20
0.15
1.20 0.20
Figure G-2 External Dimensions (FP-80B)
Rev. 3.00, 12/94, page 334 of 334
H8/3724 Series, H8/3754 Series Hardware Manual
Publication Date: 1st Edition, September 1992 3rd Edition, December 1994 Published by: Semiconductor and IC Div. Hitachi, Ltd. Edited by: Technical Document Center Hitachi Microcomputer System Ltd. Copyright (c) Hitachi, Ltd., 1992. All rights reserved. Printed in Japan.
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